公开(公告)号：US20250029874A1

公开(公告)日：2025-01-23

申请号：US18909047

申请日：2024-10-08

Applicant: Applied Materials, Inc.

Inventor： Roey Shaviv ,  Suketu Arun Parikh ,  Feng Chen ,  Lu Chen

IPC: H01L21/768 ,  H01L21/02

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

公开(公告)号：US11495461B2

公开(公告)日：2022-11-08

申请号：US16800351

申请日：2020-02-25

Applicant: Applied Materials, Inc.

Inventor： Tejinder Singh ,  Suketu Arun Parikh ,  Daniel Lee Diehl ,  Michael Anthony Stolfi ,  Jothilingam Ramalingam ,  Yong Cao ,  Lifan Yan ,  Chi-I Lang ,  Hoyung David Hwang

IPC: H01L21/033 ,  H01L21/311

Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

公开(公告)号：US11177254B2

公开(公告)日：2021-11-16

申请号：US16599360

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Sanjay Natarajan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/822

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

公开(公告)号：US20200219768A1

公开(公告)日：2020-07-09

申请号：US16817983

申请日：2020-03-13

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Mihaela Balseanu

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/033

Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.

公开(公告)号：US09184333B2

公开(公告)日：2015-11-10

申请号：US13791067

申请日：2013-03-08

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Jen Shu ,  James M. Gee

IPC: H01L31/0224 ,  H01L31/18 ,  H01L21/67 ,  H01L31/0216 ,  H01L31/068

CPC classification number: H01L31/1864 ,  H01L21/67155 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521 ,  Y10T29/41

Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.

Abstract translation: 制造线包括被配置为纹理衬底的纹理化模块，被配置为形成发射极区域的发射器模块，被配置为形成钝化层的钝化层模块，被配置为形成屏障接触区域的阻挡接触模块，被配置为 将所述阻挡接触区域退火，配置成形成顶部金属接触区域的顶部金属接触模块以及被配置为将所述阻挡接触区域焊接到所述顶部金属接触区域的焊接模块。 这些模块由一个或多个自动衬底处理器集成到单个制造线中。 一种制造太阳能电池的方法包括在自动化生产线中依次进行：在衬底中掺杂掺杂剂; 设置钝化层; 处理和退火阻挡金属浆料以形成屏障接触; 并且配置和退火金属接触膏以形成顶部金属接触区域。

公开(公告)号：US12142487B2

公开(公告)日：2024-11-12

申请号：US17197969

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

公开(公告)号：US11557509B1

公开(公告)日：2023-01-17

申请号：US16691453

申请日：2019-11-21

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

公开(公告)号：US11309404B2

公开(公告)日：2022-04-19

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US11270914B2

公开(公告)日：2022-03-08

申请号：US17148982

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Mihaela Balseanu

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L21/033

Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.

公开(公告)号：US20210404062A1

公开(公告)日：2021-12-30

申请号：US17474196

申请日：2021-09-14

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh

IPC: C23C16/455 ,  H01L21/02 ,  H01L21/67

Abstract: Apparatus and methods to process one or more wafers are described. A substrate is exposed to a plurality of process stations to deposit, anneal, treat and optionally etch a film in small increments to provide self-aligned growth of the film on a substrate surface.