公开(公告)号：US11901182B2

公开(公告)日：2024-02-13

申请号：US17363810

申请日：2021-06-30

Applicant: Applied Materials, Inc.

Inventor： Xuebin Li ,  Errol Antonio C. Sanchez ,  Patricia M. Liu

IPC: H01L21/285 ,  H01L21/67 ,  H01L21/677 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/67213 ,  H01L21/67739 ,  H01L21/76876

Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

公开(公告)号：US11081358B2

公开(公告)日：2021-08-03

申请号：US16400260

申请日：2019-05-01

Applicant: Applied Materials, Inc.

Inventor： Xuebin Li ,  Errol Antonio C. Sanchez ,  Patricia M. Liu

IPC: H01L21/285 ,  H01L21/67 ,  H01L21/677 ,  H01L21/768

Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

公开(公告)号：US12062579B2

公开(公告)日：2024-08-13

申请号：US17085850

申请日：2020-10-30

Applicant: Applied Materials, Inc.

Inventor： Xuebin Li

IPC: H01L21/8238 ,  C23C16/42 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/285

CPC classification number: H01L21/823814 ,  C23C16/42 ,  C23C16/50 ,  C23C16/52 ,  H01J37/3244 ,  H01J37/32715 ,  H01J37/32834 ,  H01J2237/3321 ,  H01L21/28518

Abstract: A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer.

公开(公告)号：US11195923B2

公开(公告)日：2021-12-07

申请号：US16678526

申请日：2019-11-08

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Tushar Vidyadhar Mandrekar ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L21/44 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

公开(公告)号：US10971366B2

公开(公告)日：2021-04-06

申请号：US16417224

申请日：2019-05-20

Applicant: Applied Materials, Inc.

Inventor： Xuebin Li ,  Patricia M. Liu

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/67 ,  H01L21/28

Abstract: Methods for depositing a metal silicide are provide and include heating a substrate having a silicon-containing surface to a deposition temperature, and exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process. The deposition gas contains a silicon precursor, a titanium or other metal precursor, and a phosphorus or other non-metal precursor.

公开(公告)号：US10276688B2

公开(公告)日：2019-04-30

申请号：US15896983

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US09966271B2

公开(公告)日：2018-05-08

申请号：US15345549

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Wei Liu ,  Hua Chung ,  Xuebin Li ,  Yuxiang Lu

IPC: H01L21/302 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32009 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/02115 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/66795

Abstract: Methods for forming semiconductor devices, such as FinFET devices, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets and a bottom surface including two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed by an isotropic plasma etch process. The isotropic plasma etch process may be performed at a pressure ranging from about 5 mTorr to about 200 mTorr in order to maximize the amount of radicals while minimizing the amount of ions in the plasma. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.

公开(公告)号：US09923081B1

公开(公告)日：2018-03-20

申请号：US15479091

申请日：2017-04-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US12297559B2

公开(公告)日：2025-05-13

申请号：US17961463

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Hua Chung ,  Flora Fong-Song Chang

IPC: C30B25/18 ,  C23C16/02 ,  C23C16/24 ,  C23C16/54 ,  C23C16/56 ,  C30B29/06 ,  C30B33/12 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687

Abstract: Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

公开(公告)号：US11615986B2

公开(公告)日：2023-03-28

申请号：US17477741

申请日：2021-09-17

Applicant: Applied Materials, Inc.

Inventor： Xuebin Li ,  Wei Liu ,  Gaurav Thareja ,  Shashank Sharma ,  Patricia M. Liu ,  Schubert Chu

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/67 ,  H01L29/40 ,  H01L21/02 ,  H01L21/321 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/417

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.