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公开(公告)号：US09665447B2
公开(公告)日：2017-05-30
申请号：US14140686
申请日：2013-12-26
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Martin Peter John Cornes , Pasi Jukka Petteri Vaananen , Liu Jiang
CPC classification number: G06F11/1637 , G06F11/165
Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first chassis health signal, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first chassis health signal based on the determination. The system also includes a second FSC that continuously generates a second chassis health signal, that determines whether a copy of the data packet is valid, and that selectively determines whether to de-assert the second chassis health signal based on the determination. The system further includes a safety relay box module that determines whether to instruct the first FSC to operate in a predetermined mode based on the first chassis health signal and the second chassis health signal.
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公开(公告)号：US09311212B2
公开(公告)日：2016-04-12
申请号：US14141594
申请日：2013-12-27
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Pasi Jukka Petteri Vaananen , Martin Peter John Cornes , Liu Jiang
CPC classification number: G06F11/3409 , G06F11/1633 , G06F11/165
Abstract: A system includes a first application that writes a first plurality of tasks to a first memory buffer; a second memory buffer that receives a copy of the first plurality of tasks; a second application that writes a second plurality of tasks to a third memory buffer; and a fourth memory buffer that receives a copy of the second plurality of tasks. The system further includes a first comparison module that generates a first voting signal based on a first comparison between a first task and a second task. The system further includes a second comparison module that generates a second voting signal based on a second comparison between the first task and the second task. The system further includes a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.
Abstract translation: 系统包括将第一多个任务写入第一存储器缓冲器的第一应用程序; 第二存储器缓冲器，其接收所述第一多个任务的副本; 将第二多个任务写入第三存储器缓冲器的第二应用程序; 以及第四存储器缓冲器，其接收第二多个任务的副本。 该系统还包括第一比较模块，其基于第一任务和第二任务之间的第一比较来生成第一投票信号。 该系统还包括第二比较模块，其基于第一任务和第二任务之间的第二比较来生成第二投票信号。 该系统还包括第一中央处理单元（CPU），其基于第一投票信号和第二投票信号选择性地确定是否去除模块健康信号。
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Patent Agency Ranking
公开(公告)号：US09791901B2
公开(公告)日：2017-10-17
申请号：US14141580
申请日：2013-12-27
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Robert Charles Tufford , Liu Jiang , Pasi Jukka Petteri Vaananen , Martin Peter John Cornes
CPC classification number: G06F1/189 , G05B19/048 , G05B19/05 , G06F11/181 , G06F11/182
Abstract: A dual redundant computer safety relay box system includes first and second fail-safe computing systems (FSCs) individually mounted to first and second printed circuit boards. Each FSC includes two computing modules (CPUs) designated as a first CPU and a second CPU. The first and second FSC's are both connected to a safety relay box. The printed circuit boards are isolable from each other permitting maintenance on one of the printed circuit boards while operation of the FSC of the other printed circuit board is maintained. In each FSC a health signal generated from the first and second printed circuit boards of the first and second CPUs defines a multi-level dynamic pulse signal. Presence of the dynamic pulse signal produces an output identified as each of a first and a second healthy indication signal from each of the CPUs of one of the first or second FSCs.
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公开(公告)号：US09497099B2
公开(公告)日：2016-11-15
申请号：US14219057
申请日：2014-03-19
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Pasi Jukka Petteri Vaananen , Martin Peter John Cornes
CPC classification number: H04L43/50 , B61L15/0063 , B61L27/0061 , G06F11/277 , G06F21/54 , G06F2201/83 , H04L63/123 , H04L69/22
Abstract: A fault-tolerant failsafe computer voting system includes a switch module that generates a first copy of a first data packet and a second copy of the first data packet and that communicates the first copy and the second copy. The system also includes a first voting module that generates a first packet signature based on the first copy and communicates the first packet signature. The system further includes a second voting module that generates a second packet signature based on the second copy and communicates the second packet signature.
Abstract translation: 容错故障安全计算机投票系统包括交换模块，其生成第一数据分组的第一副本和第一数据分组的第二副本，并且传送第一副本和第二副本。 该系统还包括第一投票模块，其基于第一副本生成第一包签名并传送第一包签名。 所述系统还包括第二投票模块，所述第二投票模块基于所述第二副本生成第二分组签名并传送所述第二分组签名。
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公开(公告)号：US10042812B2
公开(公告)日：2018-08-07
申请号：US15148271
申请日：2016-05-06
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Shugao Ye , Liu Jiang , Kai Hu , Martin Peter John Cornes , Pasi Jukka Petteri Vaananen
IPC: G06F12/00 , G06F15/173 , G06F9/52 , G06F12/06
Abstract: A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.
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公开(公告)号：US10120772B2
公开(公告)日：2018-11-06
申请号：US15651023
申请日：2017-07-17
Applicant: Artesyn Embedded Computing, Inc.
Abstract: A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.
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7.发明授权Reliable, low latency hardware and software inter-process communication channel for safety critical system 有权可靠，低延迟的硬件和软件进程间通信通道，用于安全关键系统公开(公告)号：US09317359B2
公开(公告)日：2016-04-19
申请号：US14219051
申请日：2014-03-19
Applicant: Artesyn Embedded Computing, Inc.
Inventor： Pasi Jukka Petteri Vaananen , Martin Peter John Cornes
Abstract: A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.
Abstract translation: 包括处理器间通信信道的容错故障安全计算机系统包括传输控制模块，其对第一数据分组进行编码，并传送第一数据分组的第一编码副本和第一数据分组的第二编码副本。 该系统还包括接收器控制模块，i）接收第二数据分组的第一编码副本和第二数据分组的第二编码副本，以及ii）解码第一编码副本和第二编码副本。 该系统还包括重复数据删除模块，其接收多个数据分组并传送多个数据分组中的至少一个唯一数据分组。
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