公开(公告)号：US20130075722A1

公开(公告)日：2013-03-28

申请号：US13613192

申请日：2012-09-13

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/7869

Abstract: A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.

Abstract translation: 提供了一种用于高速响应和高速驱动半导体器件的高度可靠的结构，其中晶体管的导通状态特性增加。 在共面晶体管中，依次层叠氧化物半导体层，包括第一导电层和第二导电层的堆叠的源极和漏极电极层，栅极绝缘层和栅极电极层。 栅极电极层与第一导电层重叠，栅极绝缘层设置在它们之间，并且与其间设置有栅极绝缘层的第二导电层不重叠。

公开(公告)号：US20120267709A1

公开(公告)日：2012-10-25

申请号：US13446026

申请日：2012-04-13

Applicant: Atsuo ISOBE ,  Toshinari SASAKI

Inventor： Atsuo ISOBE ,  Toshinari SASAKI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Abstract translation: 提供高度可靠的半导体器件。 提供一种防止缺陷并实现小型化的半导体器件。 形成与包括沟槽的绝缘层接触的用作源区或漏区的区域的厚度大于用作沟道形成区的区的厚度的氧化物半导体层。 在包括氧化物半导体层的晶体管中，可以抑制阈值电压的变化，电特性的劣化和正常的导通，可以降低源电阻或漏极电阻，从而晶体管可以具有高的可靠性。

公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

Applicant: Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

Inventor： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC: H01L27/105

CPC classification number: H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Abstract translation: 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20100237354A1

公开(公告)日：2010-09-23

申请号：US12794120

申请日：2010-06-04

Applicant: Yoshiaki YAMAMOTO ,  Koichiro TANAKA ,  Atsuo ISOBE ,  Daisuke OHGARANE ,  Shunpei YAMAZAKI

Inventor： Yoshiaki YAMAMOTO ,  Koichiro TANAKA ,  Atsuo ISOBE ,  Daisuke OHGARANE ,  Shunpei YAMAZAKI

IPC: H01L29/786

CPC classification number: H01L21/6835 ,  H01L21/02532 ,  H01L21/02683 ,  H01L21/02691 ,  H01L21/84 ,  H01L23/544 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L27/12 ,  H01L29/78603 ,  H01L29/78648 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01Q1/38 ,  H01Q9/285 ,  H01Q23/00 ,  Y10S438/982 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract translation: 本发明的目的是提供一种通过与专利文献1中公开的方法不同的方法从衬底分离薄膜晶体管和包括薄膜晶体管的电路或半导体器件的方法，并且将薄膜 晶体管，以及电路或半导体器件到具有柔性的衬底。 根据本发明，在绝缘膜上形成大的开口或多个开口，在开口处形成连接到薄膜晶体管的导电膜，并且去除剥离层，然后，将具有薄的 薄膜晶体管转置到具有导电膜等的基板上。 根据本发明的薄膜晶体管具有通过激光照射而结晶的半导体膜，并且防止剥离层在不被激光照射的激光照射下曝光。

公开(公告)号：US20090078970A1

公开(公告)日：2009-03-26

申请号：US12209696

申请日：2008-09-12

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

IPC: H01L27/12

CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2224/80001

Abstract: A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.

Abstract translation: 示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。 多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。 多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。 此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

公开(公告)号：US20080142921A1

公开(公告)日：2008-06-19

申请号：US11955496

申请日：2007-12-13

Applicant: Atsuo ISOBE ,  Suguru OZAWA

Inventor： Atsuo ISOBE ,  Suguru OZAWA

IPC: H01L27/12 ,  H01L21/22

CPC classification number: H01L27/1266 ,  H01L27/124 ,  H01L29/458

Abstract: To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening. Since the second impurity element is added through the second opening, the periphery of the second opening is also doped with a slight amount of the second impurity element. Therefore, the first impurity region and the second wiring are located away a short distance from each other such that they are not shorted.

Abstract translation: 为了制造由于寄生电阻引起的导通电流的降低被抑制的肖特基势垒二极管，抑制了导通电流的变化，抑制了关断电流的增大。 该制造方法包括形成岛状半导体膜的步骤; 用第一杂质元素掺杂岛状半导体膜以形成第一杂质区; 形成绝缘膜以覆盖岛状半导体膜; 蚀刻绝缘膜以形成部分地暴露第一杂质区的第一开口和第二开口; 在所述绝缘膜上形成掩模以覆盖所述第一开口并暴露所述第二开口; 用第二杂质元素掺杂第一杂质区以形成第二杂质区; 以及形成与在所述第一开口处暴露的所述第一杂质区域接触的第一布线，以及形成与在所述第二开口处露出的所述第二杂质区域接触的第二布线。 由于通过第二开口添加第二杂质元素，所以第二开口的周边也掺杂有少量的第二杂质元素。 因此，第一杂质区域和第二布线彼此距离很短，使得它们不短路。

公开(公告)号：US20080036935A1

公开(公告)日：2008-02-14

申请号：US11872402

申请日：2007-10-15

Applicant: Hiroshi SHIBATA ,  Atsuo ISOBE

Inventor： Hiroshi SHIBATA ,  Atsuo ISOBE

IPC: G02F1/133

CPC classification number: H01L27/1248 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/40 ,  H01L27/124 ,  H01L27/1255

Abstract: To provide a liquid crystal display device having high quality display with a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a layer that is different from a gate electrode so that the capacitor wiring is arranged in parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of adjacent pixels can be avoided, thereby obtaining satisfactory display images.

Abstract translation: 为了提供具有高开口率的高质量显示的液晶显示装置，同时确保足够的存储电容器（Cs），并且同时通过将电容器布线的负载（像素写入电流）分散在 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，使得电容器布线与信号线并联布置。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US20070011520A1

公开(公告)日：2007-01-11

申请号：US11421634

申请日：2006-06-01

Applicant: Takayuki IKEDA ,  Atsuo ISOBE ,  Yoshiyuki KUROKAWA

Inventor： Takayuki IKEDA ,  Atsuo ISOBE ,  Yoshiyuki KUROKAWA

IPC: H01L21/66 ,  G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2882

Abstract: A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a semiconductor device such as a display device, and the plurality of oscillation circuits for evaluation can be tested by the measuring output terminal. Then, the measurement results are Fourier transformed to obtain the oscillation frequency of the plurality of oscillation circuits for evaluation at the same time. Thus, variations in semiconductor elements can be evaluated.

Abstract translation: 提供使用多个用于评估的振荡电路的测试电路和测试方法，以便减少测量时间并简化测试。 一个测量端子由用于评估的多个振荡电路共享，所述振荡电路形成在与诸如显示装置的半导体器件相同的衬底上，并且可以通过测量输出端子来测试用于评估的多个振荡电路。 然后，将测量结果进行傅里叶变换，以同时获得用于评估的多个振荡电路的振荡频率。 因此，可以评估半导体元件的变化。

公开(公告)号：US20130075721A1

公开(公告)日：2013-03-28

申请号：US13613178

申请日：2012-09-13

Applicant: Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

IPC: H01L29/12

CPC classification number: H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/10 ,  H01L29/41733 ,  H01L29/41775

Abstract: Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

Abstract translation: 提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。 晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。 此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

公开(公告)号：US20130069054A1

公开(公告)日：2013-03-21

申请号：US13608042

申请日：2012-09-10

Applicant: Atsuo ISOBE ,  Toshinari SASAKI

Inventor： Atsuo ISOBE ,  Toshinari SASAKI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/1225 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/7869

Abstract: In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer.

Abstract translation: 在包括氧化物半导体层的半导体器件中，形成与氧化物半导体层的下部接触的导电层，并且进行用于添加杂质的处理，使得沟道形成区域和一对低电阻区域在 在自对准的方式在氧化物半导体层中形成夹着沟道形成区域的区域。 电连接到导电层和低电阻区域的接线层设置在绝缘层的开口中。