公开(公告)号：US09934160B1

公开(公告)日：2018-04-03

申请号：US15217947

申请日：2016-07-22

Applicant: BiTMICRO LLC

Inventor： Cyrill C. Ponce ,  Marizonne Operio Fuentes ,  Gianico Geonzon Noble

IPC: G06F3/00 ,  G06F12/1081 ,  G11C7/10 ,  G06F13/28 ,  G06F13/16 ,  G06F12/0875 ,  G06F3/06

CPC classification number: G06F12/1081 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/28 ,  G06F2212/452 ,  G11C7/1072

Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

公开(公告)号：US10540242B2

公开(公告)日：2020-01-21

申请号：US16248419

申请日：2019-01-15

Applicant: BITMICRO LLC

Inventor： Rolando H. Bruce ,  Richard A. Cantong ,  Marizonne Operio Fuentes

IPC: G06F11/00 ,  G06F11/14 ,  G06F3/06 ,  G06F12/0804

Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.

公开(公告)号：US20190220373A1

公开(公告)日：2019-07-18

申请号：US16248419

申请日：2019-01-15

Applicant: BITMICRO LLC

Inventor： Rolando H. Bruce ,  Richard A. Cantong ,  Marizonne Operio Fuentes

IPC: G06F11/14 ,  G06F3/06 ,  G06F12/0804

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/1435 ,  G06F11/1438 ,  G06F12/0804 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85 ,  G06F2212/1032

Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data,