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    Electroplating system and pressure device thereof
    1.
    发明授权
    Electroplating system and pressure device thereof 有权

    公开(公告)号：US10808331B2

    公开(公告)日：2020-10-20

    申请号：US15867878

    申请日：2018-01-11

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Tsuo-Yun Chu ,  Xin-Wei Lo ,  Nian-Cih Yang

    IPC: C25D21/04 ,  C25D17/00 ,  C25D21/10 ,  C25D17/06 ,  C25D5/08

    Abstract: An electroplating system for depositing a plating material on an object includes a pressure device and an anode element. The pressure device includes a lid having first and second through holes and a base having a chamber, conduction holes and third through holes located in the chamber. Each of the conduction tubes includes a conduction hole connecting to one of the third through holes. The lid covers the chamber, the first through holes communicate with the chamber for spraying an electroplating solution toward the object and the second through holes reveal the conduction holes. A passage of electric force line is formed in the connected holes and the third through holes filled with the electroplating solution, and the anode element is located outside the passage of electric force line. The electroplating system can prevent defective plating and enhance plating efficiency.

    Surface acoustic wave device and method of manufacturing the same
    2.
    发明授权
    Surface acoustic wave device and method of manufacturing the same 有权

    公开(公告)号：US11522517B2

    公开(公告)日：2022-12-06

    申请号：US16581901

    申请日：2019-09-25

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Cheng-Fan Lin

    IPC: H03H9/02 ,  H01L41/047 ,  H03H9/05 ,  H03H9/145

    Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

    Chip package and chip thereof
    3.
    发明授权
    Chip package and chip thereof 有权

    公开(公告)号：US10797213B2

    公开(公告)日：2020-10-06

    申请号：US16260528

    申请日：2019-01-29

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chin-Tang Hsieh ,  Cheng-Hung Shih

    IPC: H01L33/62 ,  H01L33/38

    Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

    ELECTROPLATING SYSTEM AND PRESSURE DEVICE THEREOF
    4.
    发明申请
    ELECTROPLATING SYSTEM AND PRESSURE DEVICE THEREOF 审中-公开

    公开(公告)号：US20190186037A1

    公开(公告)日：2019-06-20

    申请号：US15867878

    申请日：2018-01-11

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Tsuo-Yun Chu ,  Xin-Wei Lo ,  Nian-Cih Yang

    IPC: C25D21/04 ,  C25D17/06 ,  C25D5/08

    Abstract: An electroplating system for depositing a plating material on an object includes a pressure device and an anode element. The pressure device includes a lid having first and second through holes and a base having a chamber, conduction holes and third through holes located in the chamber. Each of the conduction tubes includes a conduction hole connecting to one of the third through holes. The lid covers the chamber, the first through holes communicate with the chamber for spraying an electroplating solution toward the object and the second through holes reveal the conduction holes. A passage of electric force line is formed in the connected holes and the third through holes filled with the electroplating solution, and the anode element is located outside the passage of electric force line. The electroplating system can prevent defective plating and enhance plating efficiency.

    CHIP STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    CHIP STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250038052A1

    公开(公告)日：2025-01-30

    申请号：US18611848

    申请日：2024-03-21

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Chia-Ling Shih

    IPC: H01L21/78 ,  H01L21/48 ,  H01L21/683 ,  H01L23/367

    Abstract: In a method of manufacturing a chip structure, a first carrier is attached on a back surface of a wafer, the wafer is diced into individual dies and there is a groove formed between the adjacent dies, then a second carrier is attached on an active surface of the wafer and the first carrier is removed to expose the groove, a back surface and a lateral surface of each of the dies, a heat dissipation cover is formed on the back surface and the lateral surface of each of the dies to obtain chip structures. The heat dissipation cover is provided to increase heat dissipation efficiency of the dies and prevent formation of metal debris which may contaminate the dies. Furthermore, the heat dissipation cover is prevented from being separated from the die.

    Storage container for electronic devices
    7.
    发明授权
    Storage container for electronic devices 有权

    公开(公告)号：US11148864B1

    公开(公告)日：2021-10-19

    申请号：US17169653

    申请日：2021-02-08

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Tsuo-Yun Chu

    IPC: B65D81/05 ,  B65D25/10 ,  B65D85/38

    Abstract: The present invention discloses a storage container for electronic devices, especially for wafer frames. The storage container includes a body and a stop rod that is provided to open or close a pick-and-place path in the body. The pick-and-place path is open to allow the wafer frames placed in the body to be taken out when a recess of the stop rod is located in the pick-and-place path. On the contrary, the pick-and-place path is closed when a blocking part of the stop rod is located in the pick-and-place path so as to protect the wafer frames placed in the body from falling out from the storage container.

    Semiconductor package structure having hollow chamber and bottom substrate and package process thereof
    9.
    发明授权
    Semiconductor package structure having hollow chamber and bottom substrate and package process thereof 有权
    具有中空室和底部基板的半导体封装结构及其封装工艺

    公开(公告)号：US09508676B1

    公开(公告)日：2016-11-29

    申请号：US14848439

    申请日：2015-09-09

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Fu-Yen Ho ,  Yen-Ting Chen

    IPC: H01L23/00

    CPC classification number: H01L24/83 ,  H01L21/50 ,  H01L23/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/14179 ,  H01L2224/16245 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/165

    Abstract: A semiconductor package structure having hollow chamber includes a bottom substrate having a bottom baseboard and a bottom metal layer formed on a disposing area of the bottom baseboard, a connection layer formed on the bottom metal layer, and a top substrate. The bottom metal layer has at least one corner having a first and a second outer lateral surface, and an outer connection surface. A first extension line is formed from a first extreme point of the first outer lateral surface, and a second extension line is formed from a second extreme point of the second outer lateral surface. A first exposing area of the bottom baseboard is formed by connecting the first and second extreme points and a cross point of the first and second extreme points. The top substrate connects to the connection layer to form a hollow chamber between the top and bottom substrates.

    Abstract translation: 具有中空室的半导体封装结构包括：底部基板，具有形成在底部基板的设置区域上的底部基板和底部金属层，形成在底部金属层上的连接层和顶部基板。 底部金属层具有至少一个具有第一和第二外侧表面的角部和外部连接表面。 第一延伸线由第一外侧表面的第一极点形成，第二延伸线由第二外侧表面的第二极限点形成。 通过连接第一极点和第二极值点以及第一和第二极值点的交叉点来形成底部基板的第一暴露区域。 顶部衬底连接到连接层，以在顶部和底部衬底之间形成中空室。

    TRACE STRUCTURE OF FINE-PITCH PATTERN
    10.
    发明申请
    TRACE STRUCTURE OF FINE-PITCH PATTERN 审中-公开
    精细图案的追踪结构

    公开(公告)号：US20160020166A1

    公开(公告)日：2016-01-21

    申请号：US14515719

    申请日：2014-10-16

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Yung-Wei Hsieh ,  Cheng-Hung Shih ,  Kai-Yi Wang ,  Heh-Chang Huang ,  Po-Hao Chen

    IPC: H01L23/50

    CPC classification number: H01L23/49838 ,  H01L21/4846

    Abstract: A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues.

    Abstract translation: 细间距图案的迹线结构包括连接部分，第一导线部分和第二导线部分，第一导线部分包括连接到第一部分的第一部分和第二部分，第一部分连接到 连接部分，第二导线部分包括连接到第三部分的第三部分和第四部分，第三部分连接到连接部分，其中通过连接部分，第三部分和第三部分形成三面封闭的蚀刻空间， 所述第一部分在所述第三部分和所述第一部分之间限定第一间隔，在所述第四部分和所述第二部分之间限定第二间隔，其中所述第一间隔大于所述第二间隔，以使所述第一部分内的金属层在 蚀刻空间完全去除以避免金属层残留。

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