公开(公告)号：US09841487B2

公开(公告)日：2017-12-12

申请号：US14928062

申请日：2015-10-30

Applicant: CHROMA ATE INC.

Inventor： Hou-Chun Chen ,  Shin-Wen Lin ,  Ching-Hua Chu ,  Po-Kai Cheng

IPC: G01R31/00 ,  G01R35/00 ,  G01R31/28

CPC classification number: G01R35/005 ,  G01R31/2834 ,  G01R31/2882

Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.

公开(公告)号：US09647650B2

公开(公告)日：2017-05-09

申请号：US14971044

申请日：2015-12-16

Applicant: CHROMA ATE INC.

Inventor： Cheng-Hsien Chang ,  Ching-Hua Chu ,  Shin-Wen Lin

IPC: H03K5/135 ,  G06F1/04 ,  H03K5/00

CPC classification number: H03K5/135 ,  G06F1/04 ,  G06F1/06 ,  H03K2005/00078

Abstract: A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.