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    RECESSED FIELD PLATE TRANSISTOR STRUCTURES
    3.
    发明申请
    RECESSED FIELD PLATE TRANSISTOR STRUCTURES 有权
    残余场板晶体管结构

    公开(公告)号：US20140361342A1

    公开(公告)日：2014-12-11

    申请号：US13929487

    申请日：2013-06-27

    Applicant: CREE, INC.

    Inventor： Saptharishi Sriram ,  Terry Alcorn ,  Fabian Radulescu ,  Scott Sheppard

    IPC: H01L29/778

    CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7787

    Abstract: A transistor device including a field plate is described. One embodiment of such a device includes a field plate separated from a semiconductor layer by a thin spacer layer. In one embodiment, the thickness of spacer layer separating the field plate from the semiconductor layers is less than the thickness of spacer layer separating the field plate from the gate. In another embodiment, the non-zero distance separating the field plate from the semiconductor layers is about 1500 Å or less. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.

    Abstract translation: 描述包括场板的晶体管器件。 这种器件的一个实施例包括通过薄间隔层从半导体层分离的场板。 在一个实施例中，将场板与半导体层分离的间隔层的厚度小于将场板与栅极分离的间隔层的厚度。 在另一个实施例中，将场板与半导体层分开的非零距离为约1500或更小。 根据本发明的器件可以显示依赖于较少漏极偏置的电容，导致改善的线性度。

    CASCODE STRUCTURES FOR GaN HEMTs
    6.
    发明申请
    CASCODE STRUCTURES FOR GaN HEMTs 有权
    GaN HEMT的CASCODE结构

    公开(公告)号：US20140361341A1

    公开(公告)日：2014-12-11

    申请号：US13913490

    申请日：2013-06-09

    Applicant: CREE, INC.

    Inventor： Saptharishi Sriram ,  Terry Alcorn ,  Fabian Radulescu ,  Scott Sheppard

    IPC: H01L29/423 ,  H01L29/778

    CPC classification number: H01L29/42356 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7787

    Abstract: A multi-stage transistor device is described. One embodiment of such a device is a dual-gate transistor, where the second stage gate is separated from a barrier layer by a thin spacer layer and is grounded through a connection to the source. In one embodiment the thin spacer layer and the second stage gate are placed in an aperture in a spacer layer. In another embodiment, the second stage gate is separated from a barrier layer by a spacer layer. The device can exhibit improved linearity and reduced complexity and cost.

    Abstract translation: 描述多级晶体管器件。 这种器件的一个实施例是双栅晶体管，其中第二级栅极通过薄间隔层与阻挡层分离，并且通过与源极的连接而接地。 在一个实施例中，薄间隔层和第二级门被放置在间隔层中的孔中。 在另一个实施例中，第二级栅极通过间隔层与阻挡层分开。 该装置可以显示出改进的线性度并降低复杂性和成本。

    FIELD EFFECT TRANSISTOR WITH ENHANCED RELIABILITY
    8.
    发明申请
    FIELD EFFECT TRANSISTOR WITH ENHANCED RELIABILITY 有权

    公开(公告)号：US20220130985A1

    公开(公告)日：2022-04-28

    申请号：US17325576

    申请日：2021-05-20

    Applicant: Cree, Inc.

    Inventor： Kyle Bothe ,  Terry Alcorn ,  Dan Namishia ,  Jia Guo ,  Matt King ,  Saptharishi Sriram ,  Jeremy Fisher ,  Fabian Radulescu ,  Scott Sheppard ,  Yueying Liu

    IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

    Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ΓD. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ΓD is less than about 0.3 μm, and the distance d1 is less than about 80 nm.

    Stepped field plates with proximity to conduction channel and related fabrication methods
    10.
    发明授权
    Stepped field plates with proximity to conduction channel and related fabrication methods 有权

    公开(公告)号：US11075271B2

    公开(公告)日：2021-07-27

    申请号：US16600825

    申请日：2019-10-14

    Applicant: Cree, Inc.

    Inventor： Evan Jones ,  Terry Alcorn ,  Jia Guo ,  Fabian Radulescu ,  Scott Sheppard

    IPC: H01L29/40 ,  H01L29/66 ,  H01L29/778

    Abstract: A transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent the gate and a second portion adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion of the gate. Related devices and fabrication methods are also discussed.

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