公开(公告)号：US20160099347A1

公开(公告)日：2016-04-07

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/426 ,  H01L21/027

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

Abstract translation: 本发明提供一种横向扩散的金属氧化物半导体器件的制造方法，包括以下步骤：在晶片的基板上生长氧化物层（S210）; 在晶片的表面上涂覆光致抗蚀剂（S220）; 通过使用第一光刻掩模进行光蚀刻，以及在显影后曝光第一植入窗口（S230）; 经由所述第一注入窗进行离子注入以在所述衬底中形成漂移区（S240）; 在去除光致抗蚀剂之后再次在晶片表面上涂覆一层光致抗蚀剂（S250）; 通过使用漂移区域的氧化物层的光刻掩模来执行光刻（S260）; 并蚀刻氧化层以形成漂移区的氧化物层（S270）。 还提供了横向扩散的金属氧化物半导体器件。

公开(公告)号：US09865702B2

公开(公告)日：2018-01-09

申请号：US15541155

申请日：2015-09-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Feng Huang ,  Guangtao Han ,  Guipeng Sun ,  Feng Lin ,  Longjie Zhao ,  Huatang Lin ,  Bing Zhao ,  Lixiang Liu ,  Liangliang Ping ,  Fengying Chen

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/66325 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/26513 ,  H01L21/31116 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7393 ,  H01L29/78

Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).

公开(公告)号：US09768292B2

公开(公告)日：2017-09-19

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/426

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

公开(公告)号：US20150137192A1

公开(公告)日：2015-05-21

申请号：US14407599

申请日：2013-06-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han

IPC: H01L29/808 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/808 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402

Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

Abstract translation: 本发明公开了一种高电压JFET。 高电压JFET包括位于第一导电型外延层上的第二导电类型漂移区; 位于所述第二导电型漂移区域中的第二导电型漏极重掺杂区域; 位于所述第二导电型漂移区和所述第二导电型漏极重掺杂区的一侧的漏极端氧区; 位于第二导电型漂移区侧的第一导电型阱区; 第二导电型源极重掺杂区域和位于第一导电类型阱区域上的第一导电类型栅极重掺杂区域和栅极源极氧区域; 位于所述第二导电型源极重掺杂区域和所述第二导电型漂移区域之间的第二导电型沟道层; 位于第二导电型沟道层上的电介质层和场电极板。 其中漏极电极从第二导电类型漏极重掺杂区域引出; 源极电极从场电极板和第二导电类型源重掺杂区域的连接引出; 并且从第一导电型栅极重掺杂区域引出栅电极。 晶体管具有高击穿电压，易于集成。

公开(公告)号：US09947785B2

公开(公告)日：2018-04-17

申请号：US15318857

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/47 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/808

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/66901 ,  H01L29/782 ,  H01L29/808

Abstract: The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

公开(公告)号：US09716169B2

公开(公告)日：2017-07-25

申请号：US14902261

申请日：2014-08-15

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Feng Huang ,  Guipeng Sun ,  Guangtao Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7816 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

Abstract: A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.

公开(公告)号：US09543451B2

公开(公告)日：2017-01-10

申请号：US14407599

申请日：2013-06-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han

IPC: H01L29/808 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/808 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402

Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

Abstract translation: 本发明公开了一种高电压JFET。 高电压JFET包括位于第一导电型外延层上的第二导电类型漂移区; 位于所述第二导电型漂移区域中的第二导电型漏极重掺杂区域; 位于所述第二导电型漂移区和所述第二导电型漏极重掺杂区的一侧的漏极端氧区; 位于第二导电型漂移区侧的第一导电型阱区; 第二导电型源极重掺杂区域和位于第一导电类型阱区域上的第一导电类型栅极重掺杂区域和栅极源极氧区域; 位于所述第二导电型源极重掺杂区域和所述第二导电型漂移区域之间的第二导电型沟道层; 位于第二导电型沟道层上的电介质层和场电极板。 其中漏极电极从第二导电类型漏极重掺杂区域引出; 源极电极从场电极板和第二导电类型源重掺杂区域的连接引出; 并且从第一导电型栅极重掺杂区域引出栅电极。 晶体管具有高击穿电压，易于集成。