公开(公告)号：US11951122B2

公开(公告)日：2024-04-09

申请号：US17390048

申请日：2021-07-30

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: A61K31/716 ,  A61K9/00 ,  A61K45/06 ,  A61P1/12 ,  C12P19/04 ,  C12R1/02

CPC classification number: A61K31/716 ,  A61K9/0053 ,  A61K45/06 ,  A61P1/12 ,  C12P19/04 ,  C12R2001/02

Abstract: Provided is a use of fibers formed of β-1-4-glucan in manufacturing a composition for preventing or treating diarrhea, constipation or irritable bowel syndrome, wherein the fibers have a diameter between 15 nm to 35 nm and a mean length of between 1.5 μm and 3.5 μm. Also provided is a method for preventing or treating diarrhea, constipation or irritable bowel syndrome with the fibers formed of β-1-4-glucan.

公开(公告)号：US08932962B2

公开(公告)日：2015-01-13

申请号：US13442040

申请日：2012-04-09

Applicant: Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L21/302

CPC classification number: H01L21/6708 ,  H01L21/30608 ,  H01L21/31111 ,  H01L21/67109 ,  H01L22/12 ,  H01L22/20

Abstract: A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.

Abstract translation: 用于将液体蚀刻剂分配到晶片上的方法和设备使用扫描分配喷嘴将液体蚀刻剂分配到晶片上，同时根据分配喷嘴在晶片上的径向位置实时控制蚀刻剂的分配温度。 控制蚀刻剂的分配温度以提高蚀刻剂的有效性，从而补偿晶片中较低的蚀刻速率区域。

公开(公告)号：US20130320410A1

公开(公告)日：2013-12-05

申请号：US13484047

申请日：2012-05-30

Applicant: Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及金属栅电极。 半导体器件的示例性结构包括：包括主表面的衬底; 主表面上的第一矩形栅电极，包括第一层多层材料; 与第一矩形栅电极的一侧相邻的第一电介质材料; 以及与所述第一矩形栅电极的其他3侧相邻的第二电介质材料，其中所述第一电介质材料和所述第二电介质材料共同围绕所述第一矩形栅电极。

公开(公告)号：US08507979B1

公开(公告)日：2013-08-13

申请号：US13563470

申请日：2012-07-31

Applicant: Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括提供半导体衬底并在其中形成栅极沟槽。 该方法还包括用工作功能（WF）金属堆叠部分地填充栅极沟槽，并且在WF金属堆叠上用虚拟填充材料（DFM）填充剩余的栅极沟槽。 通过蚀刻在栅极沟槽中的WF金属堆叠形成子栅极沟槽，并且填充有绝缘体帽以在栅极沟槽中形成隔离区域。 DFM从栅极沟槽中的MG-中心沟槽（MGCT）被完全去除，其填充有填充金属。

公开(公告)号：US20120149171A1

公开(公告)日：2012-06-14

申请号：US13399488

申请日：2012-02-17

Applicant: Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

Inventor： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC: H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76232

Abstract: A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

Abstract translation: 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US20110147810A1

公开(公告)日：2011-06-23

申请号：US12645834

申请日：2009-12-23

Applicant: Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen

Inventor： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，设置在衬底的一部分上的栅极结构以及设置在衬底的该部分的任一侧的应变结构，并且由与半导体衬底不同的半导体材料形成。 衬底的部分是具有水平区域的垂直区域和从远离衬底表面的方向从水平区域延伸的垂直区域。

公开(公告)号：US07833853B2

公开(公告)日：2010-11-16

申请号：US12339483

申请日：2008-12-19

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

IPC: H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract translation: 提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。 栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。 该方法包括在衬底上形成覆盖层并覆盖栅极结构。 将涂层回蚀刻以露出栅极结构的一部分。 蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

公开(公告)号：US20070040188A1

公开(公告)日：2007-02-22

申请号：US11207450

申请日：2005-08-19

Applicant: Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L31/00

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract translation: 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US07169701B2

公开(公告)日：2007-01-30

申请号：US10882058

申请日：2004-06-30

Applicant: Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

Inventor： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76801 ,  H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1031

Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

Abstract translation: 一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在所述有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。

公开(公告)号：US20050106856A1

公开(公告)日：2005-05-19

申请号：US10714304

申请日：2003-11-14

Applicant: Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

Inventor： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31695

Abstract: A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

Abstract translation: 一种形成双镶嵌开口的方法，包括以下步骤。 提供一种其上形成有上覆的暴露的导电层的结构。 在暴露的导电层上形成电介质层。 在电介质层上形成抗反射涂层。 使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。 至少在导电层的暴露部分上形成保护膜部分。 将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。 沟槽开口和通孔包括双镶嵌开口。