公开(公告)号：US20070057692A1

公开(公告)日：2007-03-15

申请号：US11162531

申请日：2005-09-14

Applicant: Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

Inventor： Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.

Abstract translation: 提供了用于确定至少一个驱动器的阻抗的驱动器阻抗控制装置和系统。 驱动器阻抗控制装置包括第一参考阻抗，第二参考阻抗，虚拟上拉阵列，虚拟下拉阵列，上拉阵列控制单元和下拉阵列控制单元。 上拉阵列控制单元通过检测来自第一参考阻抗和虚拟上拉阵列之间的第一分压点的电压来控制驱动器的上拉阻抗。 下拉阵列控制单元通过检测来自第二参考阻抗和虚拟下拉阵列之间的第二分压点的电压来控制驱动器的下拉阻抗。

公开(公告)号：US06728086B2

公开(公告)日：2004-04-27

申请号：US10050018

申请日：2002-01-15

Applicant: Kei-Kang Hung ,  Chien-Hui Chuang

Inventor： Kei-Kang Hung ,  Chien-Hui Chuang

IPC: H02H900

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power-rail ESD (electrostatic discharge) protection circuit with a dual trigger design is proposed, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line. The proposed power-rail ESD protection circuit comprises a control circuit and at least one MOS device. The control circuit is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage to the MOS device, causing the MOS device to bypass the ESD current from the first power line and the second power line. The circuit configuration of the proposed power-rail ESD protection circuit can help reduce the junction breakdown voltage in a MOS device and increase in ESD robustness.

Abstract translation: 提出了具有双触发设计的电力轨道ESD（静电放电）保护电路，其耦合在连接到IC装置的第一电力线和第二电力线之间，用于保护IC装置免受第一电力线上的ESD， 第二条电力线。 所提出的电源轨ESD保护电路包括控制电路和至少一个MOS器件。 控制电路耦合在第一电力线和第二电力线之间，并且其能够在第一电力线和第二电力线中的ESD的情况下被ESD触发以输出基板触发电压 以及向MOS器件施加栅极驱动电压，使MOS器件从第一电力线和第二电力线旁路ESD电流。 所提出的电力轨道ESD保护电路的电路配置有助于降低MOS器件中的结击穿电压，增加ESD稳定性。

公开(公告)号：US06639772B2

公开(公告)日：2003-10-28

申请号：US10041237

申请日：2002-01-07

Applicant: Chien-Hui Chuang ,  Kei-Kang Hung

Inventor： Chien-Hui Chuang ,  Kei-Kang Hung

IPC: H02H300

CPC classification number: H01L27/0277

Abstract: An electrostatic discharge (ESD) protection circuit for protecting input and output buffers. The ESD protection circuit is driven by a first voltage source and a second voltage source and coupled to a bonding pad. The ESD protection circuit has a first resistor, a first PMOS transistor, a first NMOS transistor, a first diode series, a second PMOS transistor, a second resistor, a third PMOS transistor, a second NMOS transistor, a second diode series and a third NMOS transistor. The electrical devices combine to form different types of ESD protection circuits, each capable of protecting the input buffer or output buffer against the damaging effects of an electrostatic discharge.

Abstract translation: 一种用于保护输入和输出缓冲器的静电放电（ESD）保护电路。 ESD保护电路由第一电压源和第二电压源驱动并耦合到接合焊盘。 ESD保护电路具有第一电阻器，第一PMOS晶体管，第一NMOS晶体管，第一二极管系列，第二PMOS晶体管，第二电阻器，第三PMOS晶体管，第二NMOS晶体管，第二二极管串联和第三 NMOS晶体管。 电气设备组合形成不同类型的ESD保护电路，每个ESD保护电路能够保护输入缓冲器或输出缓冲器免受静电放电的破坏作用。

公开(公告)号：US20100277842A1

公开(公告)日：2010-11-04

申请号：US12431779

申请日：2009-04-29

Applicant: Chien-Hui Chuang

Inventor： Chien-Hui Chuang

IPC: H02H9/02

CPC classification number: H03K19/017509 ,  H01L27/0285 ,  H03K19/00315

Abstract: A buffer device includes a first driving circuit coupled between a signal terminal of the buffer device and a first reference potential, a current-limiting component including a first terminal coupled to the signal terminal, and a second driving circuit coupled between a second terminal of the current-limiting component and a second reference potential, wherein the current-limiting component limits an amount of ESD current flowing through the second driving circuit, and makes an amount of ESD current flowing through the first driving circuit be larger than the amount of ESD current flowing through the second driving circuit.

Abstract translation: 缓冲器件包括耦合在缓冲器件的信号端和第一参考电位之间的第一驱动电路，包括耦合到信号端的第一端的限流元件和耦合在第二参考电位的第二端之间的第二驱动电路 限流部件和第二参考电位，其中所述限流部件限制流过所述第二驱动电路的ESD电流量，并且使流过所述第一驱动电路的ESD电流量大于所述ESD电流量 流经第二驱动电路。

公开(公告)号：US07339398B2

公开(公告)日：2008-03-04

申请号：US11162531

申请日：2005-09-14

Applicant: Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

Inventor： Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.

Abstract translation: 提供了用于确定至少一个驱动器的阻抗的驱动器阻抗控制装置和系统。 驱动器阻抗控制装置包括第一参考阻抗，第二参考阻抗，虚拟上拉阵列，虚拟下拉阵列，上拉阵列控制单元和下拉阵列控制单元。 上拉阵列控制单元通过检测来自第一参考阻抗和虚拟上拉阵列之间的第一分压点的电压来控制驱动器的上拉阻抗。 下拉阵列控制单元通过检测来自第二参考阻抗和虚拟下拉阵列之间的第二分压点的电压来控制驱动器的下拉阻抗。

公开(公告)号：US07050282B2

公开(公告)日：2006-05-23

申请号：US10604362

申请日：2003-07-15

Applicant: Chien-Hui Chuang ,  Hung-Yi Chang ,  Yi-Hua Chang

Inventor： Chien-Hui Chuang ,  Hung-Yi Chang ,  Yi-Hua Chang

IPC: H02H3/00 ,  H02H7/00

CPC classification number: H01L27/0285 ,  H03K17/08104

Abstract: A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.

Abstract translation: 一种电源钳位电路，用于防止由于静电放电而对集成电路造成的损坏。 电源钳位电路包括电连接到第一节点以产生电压的电压发生器; 第一PMOS晶体管，其具有电连接到第一电压源的源极，电连接到第一节点的栅极和电连接到第二节点的漏极; 第一NMOS晶体管，其具有电连接到第二节点的漏极，电连接到第一节点的栅极和连接到地的源极; 第二NMOS晶体管，其具有电连接到第一电压源的漏极，电连接到第二节点的栅极和连接到地的源极; 以及第二PMOS晶体管，其具有电连接到第二节点的源极，通常电连接到第一节点的栅极和漏极。

公开(公告)号：US20100001412A1

公开(公告)日：2010-01-07

申请号：US12168161

申请日：2008-07-07

Applicant: Tien-Chang Chang ,  Tao Cheng ,  Chien-Hui Chuang ,  Bo-Shih Huang

Inventor： Tien-Chang Chang ,  Tao Cheng ,  Chien-Hui Chuang ,  Bo-Shih Huang

IPC: H01L23/52

CPC classification number: H01L24/05 ,  H01L23/522 ,  H01L23/585 ,  H01L23/60 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.

Abstract translation: 集成电路的接合焊盘结构包括设置在第一介电层上的导电焊盘，形成在第一电介质层下面的第二电介质层中的第一导电块，并且通过形成在第一电介质层中的第一通孔插塞电连接到导电焊盘 电介质层和位于导电垫下方的电浮置的第一导电板。

公开(公告)号：US07429886B2

公开(公告)日：2008-09-30

申请号：US11324980

申请日：2006-01-03

Applicant: Jia-Jio Huang ,  Chien-Hui Chuang

Inventor： Jia-Jio Huang ,  Chien-Hui Chuang

IPC: H01H37/76 ,  H01H85/00

CPC classification number: G11C17/18

Abstract: A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

Abstract translation: 多熔丝修整电路。 多熔丝修整电路包括多晶硅熔丝和可控硅整流器（SCR）器件。 多晶硅熔丝耦合在第一固定电位和输出节点之间。 SCR器件由修整信号控制，并且具有耦合到输出节点的阳极和耦合到第二固定电位的阴极。

公开(公告)号：US06690561B2

公开(公告)日：2004-02-10

申请号：US09990453

申请日：2001-11-20

Applicant: Kei-Kang Hung ,  Chien-Hui Chuang ,  Hung-Yi Chang

Inventor： Kei-Kang Hung ,  Chien-Hui Chuang ,  Hung-Yi Chang

IPC: H02H322

CPC classification number: H02H9/046 ,  H02H3/006

Abstract: An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness. The voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.

Abstract translation: 布置在第一和第二电位端子之间的ESD保护电路具有RC分支，电压调节器电路和ESD放电晶体管。 RC分支包括从第一到第二电位端子连接的电阻器和电容器串联。 电压调节器电路具有连接到RC分支以及第一和第二电位端子的多个输入端以及连接到ESD放电晶体管的栅极的输出端，以调整其栅极电压以获得均匀的导通和最佳的ESD 健壮性 电压调节器电路主要包括多个晶体管，其能够相对于高水平的ESD应力有效地调节栅极电压。

公开(公告)号：US06657835B2

公开(公告)日：2003-12-02

申请号：US09874996

申请日：2001-06-07

Applicant: Ming-Dou Ker ,  Chien-Hui Chuang ,  Wen-Yu Lo

Inventor： Ming-Dou Ker ,  Chien-Hui Chuang ,  Wen-Yu Lo

IPC: H02H900

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor. A first terminal of the substrate current generating circuit connects to the I/O pad, a second terminal connects to the second working voltage, and a third terminal connects to the substrate of the lateral bipolar transistor, so that a triggering current is sent out of the third terminal when the voltage at the I/O pad is over a predetermined value. One end of the parasitic substrate resistor connects to the base of the bipolar transistor and the other end connects to the second working voltage, using the triggering current to generate a bias for the bipolar transistor. During ESD-stress condition, such ESD protection circuit can be quickly triggered on to discharge ESD current. During IC normal circuit operating condition, such ESD protection circuit is kept off.