公开(公告)号：US08377506B2

公开(公告)日：2013-02-19

申请号：US12574350

申请日：2009-10-06

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: B05D5/12 ,  C25D5/02 ,  C23C14/00

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/112 ,  H05K3/243 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract translation: 提供了基板结构。 基板结构包括基板，第一绝缘层，导电部件，第二绝缘层，种子层和导电层。 衬底具有分别位于衬底的两个相对表面上的第一电路图案层和第二电路图案层。 形成在第一电路图案层上的第一绝缘层具有第一绝缘孔，其暴露第一绝缘层的外表面中的第一开口。 形成在与芯片电连接的第一绝缘孔上的导电部分被第一开口的边缘包围。 形成在第二电路图案层上的第二绝缘层具有形成种子层的第二绝缘孔。 导电层形成在种子层上，用于与电路板电连接。

公开(公告)号：US08258009B2

公开(公告)日：2012-09-04

申请号：US12898728

申请日：2010-10-06

Applicant: Chih-Cheng Lee ,  Ho-Ming Tong

Inventor： Chih-Cheng Lee ,  Ho-Ming Tong

IPC: H01L21/44

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2924/15311

Abstract: A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Abstract translation: 电路基板包括以下元件。 导电层和电介质层依次设置在内部电路结构上，并且多个导电盲孔嵌入电介质层中并连接到导电层的一部分。 电镀种子层设置在每个第一盲孔和第一导电层之间。 另一导电层设置在电介质层上，其中另一导电层的一部分通过导电盲孔与导电层电连接。 第三电镀种子层设置在第三导电层和每个第一盲孔之间以及第一介电层上。

公开(公告)号：US08461461B2

公开(公告)日：2013-06-11

申请号：US12727745

申请日：2010-03-19

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: H05K1/09

CPC classification number: H05K3/045 ,  H05K3/107 ,  H05K3/465 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0723

Abstract: The present invention relates to an embedded substrate having a circuit layer element with an oblique side surface and a method for making the same. The embedded substrate includes a dielectric layer and a circuit layer element. The dielectric layer has an upper surface and an accommodating groove. The circuit layer element is disposed in the accommodating groove. The circuit layer element has an upper surface, a chemical copper layer, a plating copper layer and an oblique side surface. The elevation of the upper surface is equal to or lower than that of the upper surface of the dielectric layer. The chemical copper layer includes palladium (Pd). The plating copper layer is disposed on the chemical copper layer. The oblique side surface is disposed on the upper surface of the circuit layer element, where is close to the wall of the accommodating groove, and extends downward from the upper surface of the circuit layer element to the wall of the accommodating groove. Therefore, the oblique side surface of the circuit layer element can avoid electrons gathering at a sharp edge of a conventional circuit layer element.

Abstract translation: 本发明涉及具有倾斜侧面的电路层元件的嵌入式基板及其制造方法。 嵌入式基板包括电介质层和电路层元件。 电介质层具有上表面和容纳槽。 电路层元件设置在容纳槽中。 电路层元件具有上表面，化学铜层，镀铜层和倾斜侧表面。 上表面的高度等于或低于电介质层的上表面的高度。 化学铜层包括钯（Pd）。 电镀铜层设置在化学铜层上。 倾斜侧表面设置在电路层元件的靠近容纳槽的壁的上表面上，并且从电路层元件的上表面向下延伸到容纳槽的壁。 因此，电路层元件的倾斜侧表面可以避免电子聚集在常规电路层元件的尖锐边缘处。

公开(公告)号：US20120032331A1

公开(公告)日：2012-02-09

申请号：US12898728

申请日：2010-10-06

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2924/15311

Abstract: A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Abstract translation: 电路基板包括以下元件。 导电层和电介质层依次设置在内部电路结构上，并且多个导电盲孔嵌入电介质层中并连接到导电层的一部分。 电镀种子层设置在每个第一盲孔和第一导电层之间。 另一导电层设置在电介质层上，其中另一导电层的一部分通过导电盲孔与导电层电连接。 第三电镀种子层设置在第三导电层和每个第一盲孔之间以及第一介电层上。

公开(公告)号：US08322032B2

公开(公告)日：2012-12-04

申请号：US12720238

申请日：2010-03-09

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: H05K3/46 ,  H05K3/42 ,  H05K3/02

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/0023 ,  H05K3/04 ,  H05K3/045 ,  H05K3/06 ,  H05K3/10 ,  H05K3/108 ,  H05K3/4038 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract translation: 提供了一种用于制造衬底结构的方法。 该方法包括以下步骤。 提供基板。 衬底具有图案化的第一金属层，图案第二金属层和通孔。 之后，分别在基板的第一表面和第二表面上形成第一电介质层和第二电介质层。 第二表面与第一表面相对。 然后，对第一电介质层和第二电介质层进行图案化。 之后，在图案化的第一介电层的表面形成第一迹线层。 第一迹线层被嵌入到图案化的第一介电层中并且与第一介电层共面。 然后，在第二电介质层的表面上形成第二迹线层。

公开(公告)号：US20100288542A1

公开(公告)日：2010-11-18

申请号：US12727745

申请日：2010-03-19

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: H05K1/09 ,  C23F1/00 ,  H01B13/00 ,  C25D5/02

CPC classification number: H05K3/045 ,  H05K3/107 ,  H05K3/465 ,  H05K2203/025 ,  H05K2203/0346 ,  H05K2203/0723

Abstract: The present invention relates to an embedded substrate having a circuit layer element with an oblique side surface and a method for making the same. The embedded substrate includes a dielectric layer and a circuit layer element. The dielectric layer has an upper surface and an accommodating groove. The circuit layer element is disposed in the accommodating groove. The circuit layer element has an upper surface, a chemical copper layer, a plating copper layer and an oblique side surface. The elevation of the upper surface is equal to or lower than that of the upper surface of the dielectric layer. The chemical copper layer includes palladium (Pd). The plating copper layer is disposed on the chemical copper layer. The oblique side surface is disposed on the upper surface of the circuit layer element, where is close to the wall of the accommodating groove, and extends downward from the upper surface of the circuit layer element to the wall of the accommodating groove. Therefore, the oblique side surface of the circuit layer element can avoid electrons gathering at a sharp edge of a conventional circuit layer element.

Abstract translation: 本发明涉及具有倾斜侧面的电路层元件的嵌入式基板及其制造方法。 嵌入式基板包括电介质层和电路层元件。 电介质层具有上表面和容纳槽。 电路层元件设置在容纳槽中。 电路层元件具有上表面，化学铜层，镀铜层和倾斜侧表面。 上表面的高度等于或低于电介质层的上表面的高度。 化学铜层包括钯（Pd）。 电镀铜层设置在化学铜层上。 倾斜侧表面设置在电路层元件的靠近容纳槽的壁的上表面上，并且从电路层元件的上表面向下延伸到容纳槽的壁。 因此，电路层元件的倾斜侧表面可以避免电子聚集在常规电路层元件的尖锐边缘处。