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公开(公告)号：US20240168442A1
公开(公告)日：2024-05-23
申请号：US17989045
申请日：2022-11-17
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Ajay Bharadwaj , Romesh Kumar Nandwana
CPC classification number: G04F10/005 , H03L7/0992
Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.
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2.发明公开公开(公告)号：US20230238967A1
公开(公告)日：2023-07-27
申请号：US17582466
申请日：2022-01-24
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana
CPC classification number: H03L7/091 , H03L7/0992
Abstract: Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.
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公开(公告)号：US12191870B2
公开(公告)日：2025-01-07
申请号：US18162091
申请日：2023-01-31
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Sujit Handanhal Ramachandra
Abstract: Techniques to reduce or eliminate phase noise and jitter from a noisy clock signal. A method includes generating an electrical clock signal, generating a delayed optical clock signal based on the electrical clock signal, detecting a phase difference between the electrical clock signal and the delayed optical clock signal, and processing, based on the phase difference, the electrical clock signal to obtain a reduced phase noise version of the electrical clock signal.
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公开(公告)号：US20240259025A1
公开(公告)日：2024-08-01
申请号：US18162091
申请日：2023-01-31
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Sujit Handanhal Ramachandra
CPC classification number: H03L7/1075 , H03L7/0818
Abstract: Techniques to reduce or eliminate phase noise and jitter from a noisy clock signal. A method includes generating an electrical clock signal, generating a delayed optical clock signal based on the electrical clock signal, detecting a phase difference between the electrical clock signal and the delayed optical clock signal, and processing, based on the phase difference, the electrical clock signal to obtain a reduced phase noise version of the electrical clock signal.
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5.发明授权公开(公告)号：US11671105B2
公开(公告)日：2023-06-06
申请号：US17720446
申请日：2022-04-14
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
CPC classification number: H03L7/099 , H03B5/124 , H03B5/1212 , H03B5/1228 , H03L7/085 , H03L7/093 , H03D5/00
Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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Patent Agency Ranking
公开(公告)号：US11901906B1
公开(公告)日：2024-02-13
申请号：US17887709
申请日：2022-08-15
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
CPC classification number: H03L7/099 , G04F10/005 , G06G7/60 , G06N3/063 , H03B7/08 , H03L7/091 , H04B1/16
Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.
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公开(公告)号：US20230155618A1
公开(公告)日：2023-05-18
申请号：US17528413
申请日：2021-11-17
Applicant: Cisco Technology, Inc.
Inventor： Romesh Kumar Nandwana , Abhishek Bhat , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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8.发明授权公开(公告)号：US11356107B1
公开(公告)日：2022-06-07
申请号：US17502512
申请日：2021-10-15
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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公开(公告)号：US12147201B2
公开(公告)日：2024-11-19
申请号：US17989045
申请日：2022-11-17
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Ajay Bharadwaj , Romesh Kumar Nandwana
Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.
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公开(公告)号：US11863222B2
公开(公告)日：2024-01-02
申请号：US17528413
申请日：2021-11-17
Applicant: Cisco Technology, Inc.
Inventor： Romesh Kumar Nandwana , Abhishek Bhat , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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