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    TELEMETRY-BASED MODEL DRIVEN MANUFACTURING TEST METHODOLOGY
    2.
    发明申请
    TELEMETRY-BASED MODEL DRIVEN MANUFACTURING TEST METHODOLOGY 有权

    公开(公告)号：US20230076130A1

    公开(公告)日：2023-03-09

    申请号：US17590518

    申请日：2022-02-01

    Applicant: Cisco Technology, Inc.

    Inventor： ShiJie Wen ,  Dao-I Tony Lin ,  Anthony Winston ,  Jie Xue ,  James Edwin Turman

    IPC: G06F11/27 ,  G06F11/34

    Abstract: An approach is presented herein to use an in-situ algorithmic decision methodology during each stage of testing before 2C/4C to decide how long to test, how much margin should be used for each device under the test (DUT) to shorten or eliminate 2C/4C testing. Each DUT will be tested differently based on the risk level or the likelihood of failure at 2C/4C. To be able to achieve this, low-level hardware (HW) based sensors (on the printed circuit board assembly (PCBA), in power module, in silicon components, in silicon component complex, etc.) are used to collect telemetry data with a high frequency data acquisition rate during the testing. As testing is ongoing for each DUT, a margin distribution and algorithm modeling is performed in-situ.

    Telemetry-based model driven manufacturing test methodology
    3.
    发明授权
    Telemetry-based model driven manufacturing test methodology 有权

    公开(公告)号：US12164400B2

    公开(公告)日：2024-12-10

    申请号：US17590518

    申请日：2022-02-01

    Applicant: Cisco Technology, Inc.

    Inventor： ShiJie Wen ,  Dao-I Tony Lin ,  Anthony Winston ,  Jie Xue ,  James Edwin Turman

    IPC: G06F11/20 ,  G06F11/27 ,  G06F11/34

    Abstract: An approach is presented herein to use an in-situ algorithmic decision methodology during each stage of testing before 2C/4C to decide how long to test, how much margin should be used for each device under the test (DUT) to shorten or eliminate 2C/4C testing. Each DUT will be tested differently based on the risk level or the likelihood of failure at 2C/4C. To be able to achieve this, low-level hardware (HW) based sensors (on the printed circuit board assembly (PCBA), in power module, in silicon components, in silicon component complex, etc.) are used to collect telemetry data with a high frequency data acquisition rate during the testing. As testing is ongoing for each DUT, a margin distribution and algorithm modeling is performed in-situ.

    TELEMETRY DATA BASED COUNTERFEIT DEVICE DETECTION
    4.
    发明公开
    TELEMETRY DATA BASED COUNTERFEIT DEVICE DETECTION 审中-公开

    公开(公告)号：US20240320691A1

    公开(公告)日：2024-09-26

    申请号：US18187520

    申请日：2023-03-21

    Applicant: Cisco Technology, Inc.

    Inventor： Shi-Jie Wen ,  Dao-I Tony Lin ,  Ranjani Ram ,  Li Sun ,  James Edwin Turman ,  Anthony Winston ,  Jie Xue

    IPC: G06Q30/018 ,  H04Q9/00

    CPC classification number: G06Q30/0185 ,  H04Q9/00

    Abstract: Techniques are described for detecting counterfeit products by identifying differences between hardware components and orientations of the counterfeit products, and hardware components and orientations of authentic products. In some examples, the hardware components and orientations can be identified by generating hardware intrinsic development data based on telemetry data of products (or “devices”). By way of example, the telemetry data may be analyzed by machine learning (ML) models to generate representative models of the hardware intrinsic development data. In various examples, the representative models can include sample representative models of hardware intrinsic development data generated based on valid telemetry data of authentic devices. In those or other examples, the representative models can include other representative models (or “test representative models”) of hardware intrinsic development data generated based on unvalidated telemetry data of test devices. Comparisons between the representative models can be utilized to identify the counterfeit products.

    OPTIMIZED POWER DELIVERY FOR MULTI-LAYER SUBSTRATE
    5.
    发明申请
    OPTIMIZED POWER DELIVERY FOR MULTI-LAYER SUBSTRATE 有权

    公开(公告)号：US20230071476A1

    公开(公告)日：2023-03-09

    申请号：US17702892

    申请日：2022-03-24

    Applicant: Cisco Technology, Inc.

    Inventor： D. Brice Achkir ,  Shobhana Ram Punjabi ,  Jie Xue

    IPC: H01L23/498

    Abstract: A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.

    Optimized power delivery for multi-layer substrate
    6.
    发明授权
    Optimized power delivery for multi-layer substrate 有权

    公开(公告)号：US12057379B2

    公开(公告)日：2024-08-06

    申请号：US17702892

    申请日：2022-03-24

    Applicant: Cisco Technology, Inc.

    Inventor： D. Brice Achkir ,  Shobhana Ram Punjabi ,  Jie Xue

    IPC: H01L23/498

    CPC classification number: H01L23/49805 ,  H01L23/49822 ,  H01L23/49838

    Abstract: A multi-layer substrate stacking a plurality of insulating substrates supports one or more devices. Each substrate includes a face supporting conductive traces and edges surrounding the face at a substantially perpendicular angle. The multi-layer substrate includes a ground plane on a first substrate and a power plane on a second substrate. The ground plane is connected to at least one ground pad disposed on a first edge of the first substrate, which provides a low inductance ground path to the ground plane. The power plane is connected to at least one power pad disposed on a second edge of the second substrate, which provides a low inductance power path to the power plane.

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