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公开(公告)号：US12191915B1
公开(公告)日：2025-01-07
申请号：US17689634
申请日：2022-03-08
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Romesh Kumar Nandwana , Alexander C. Kurylak
Abstract: Techniques for implementing a differential differencing TIA for coherent applications are disclosed. A method includes receiving first and second optical signals from a 90 degree optical hybrid that receives a coherent optical signal, wherein the first and second optical signals each include one pair of sum and difference signals output by the 90 degree optical hybrid, generating, based on the first optical signal and from a first photo diode, a first differential signal, generating, based on the second optical signal and from a second photo diode, a second differential signal, differentially transconducting the first and second differential signals to produce first and second transconducted signals, performing a differencing operation on the first and second differential transconducted signals to produce a combined differential-differencing transconducted signal that is representative of the first optical signal and the second optical signal, and outputting the combined differential transconducted signal as a differential output.
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公开(公告)号：US11863222B2
公开(公告)日：2024-01-02
申请号：US17528413
申请日：2021-11-17
Applicant: Cisco Technology, Inc.
Inventor： Romesh Kumar Nandwana , Abhishek Bhat , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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公开(公告)号：US11218113B1
公开(公告)日：2022-01-04
申请号：US17031462
申请日：2020-09-24
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Kadaba Lakshmikumar
IPC: H03B5/12
Abstract: A voltage controlled oscillator (VCO) is described. The VCO includes a plurality of nodes coupled with a plurality of transistors, and a first inductor-capacitor (LC) tank coupled with a second LC tank. The first LC tank and the second LC tank include a shared inductor structure coupled to the plurality of nodes. The first LC tank and the second LC tank each include a capacitor. The capacitors are each coupled on a first side to a node of the plurality of nodes and on a second side to a respective capacitor in the other LC tank. The first LC tank and the second LC tank are configured to resonate at a fundamental frequency for differential-mode signals, and the first LC tank and the second LC tank are configured to resonate at twice the fundamental frequency for common-mode signals.
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公开(公告)号：US20200076390A1
公开(公告)日：2020-03-05
申请号：US16675629
申请日：2019-11-06
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Alexander Christopher Kurylak , Manohar Nagaraju , Richard Van Hoesen Booth
Abstract: A circuit includes a front end section configured to receive input current signals; a programmable gain amplifier section coupled to the front end section, the programmable gain amplifier section including a plurality of inverters connected in series without a resistor disposed therebetween; and an output buffer section coupled to the programmable gain amplifier section and configured to output voltage signals.
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公开(公告)号：US20160126971A1
公开(公告)日：2016-05-05
申请号：US14991467
申请日：2016-01-08
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse
Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
Abstract translation: 在一个实现中，数字模拟转换器（DAC）是单调的，因为输出仅在输入的方向上移动并被分段，因为DAC的更重要部分与较不重要的部分分离。 DAC接收包含多个最高有效位和多个最低有效位的输入二进制字。 DAC将输入二进制字解码为包括等于或大于二进制字的位宽的位宽的中间信号。 中间信号设置输出开关和电流源开关。 DAC提供表示输入二进制字的模拟输出信号。
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Patent Agency Ranking
公开(公告)号：US12126363B2
公开(公告)日：2024-10-22
申请号：US17876679
申请日：2022-07-29
Applicant: Cisco Technology, Inc.
Inventor： Bibhu Prasad Das , Romesh Kumar Nandwana , Richard Van Hoesen Booth , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
IPC: H03M3/00
Abstract: An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.
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公开(公告)号：US20240146252A1
公开(公告)日：2024-05-02
申请号：US17976991
申请日：2022-10-31
Applicant: Cisco Technology, Inc.
CPC classification number: H03F1/083 , H03F3/45475 , H03F2203/45528
Abstract: An apparatus comprises: a photodetector having a cathode and an anode to generate an output current; and a differential transimpedance amplifier (TIA) having a first amplifier input coupled to a first one of the cathode and the anode through a first AC coupling capacitor and a first feedforward resistor that is connected in parallel with the first AC coupling capacitor between the first one of the cathode and the anode and the first amplifier input, the differential TIA having a second amplifier input coupled to a second one of the cathode and the anode that is not the first one of the anode and the cathode, the differential TIA configured to convert the output current of the photodetector as presented at the first amplifier input and the second amplifier input to a differential output voltage.
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公开(公告)号：US11533057B2
公开(公告)日：2022-12-20
申请号：US17333564
申请日：2021-05-28
Applicant: Cisco Technology, Inc.
Inventor： Yudong Zhang , Romesh Kumar Nandwana , Kadaba Lakshmikumar
Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.
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公开(公告)号：US11509319B2
公开(公告)日：2022-11-22
申请号：US17115570
申请日：2020-12-08
Applicant: Cisco Technology, Inc.
Inventor： Yongxin Li , Romesh Kumar Nandwana , Kadaba Lakshmikumar
Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.
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公开(公告)号：US20210367603A1
公开(公告)日：2021-11-25
申请号：US17333564
申请日：2021-05-28
Applicant: Cisco Technology, Inc.
Inventor： Yudong Zhang , Romesh Kumar Nandwana , Kadaba Lakshmikumar
Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.
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