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    Low area equalizer with lane mismatch adaptation for sub-rate receivers
    1.
    发明授权
    Low area equalizer with lane mismatch adaptation for sub-rate receivers 有权

    公开(公告)号：US11863222B2

    公开(公告)日：2024-01-02

    申请号：US17528413

    申请日：2021-11-17

    Applicant: Cisco Technology, Inc.

    Inventor： Romesh Kumar Nandwana ,  Abhishek Bhat ,  Kadaba Lakshmikumar ,  Pavan Kumar Hanumolu

    IPC: H04B1/16 ,  H03M1/66

    CPC classification number: H04B1/16 ,  H03M1/66

    Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

    HYBRID FRACTIONAL-N SAMPLING PHASE LOCKED LOOP (PLL) WITH ACCURATE DIGITAL-TO-TIME CONVERTER (DTC) CALIBRATION
    5.
    发明公开
    HYBRID FRACTIONAL-N SAMPLING PHASE LOCKED LOOP (PLL) WITH ACCURATE DIGITAL-TO-TIME CONVERTER (DTC) CALIBRATION 审中-公开

    公开(公告)号：US20240056085A1

    公开(公告)日：2024-02-15

    申请号：US17887709

    申请日：2022-08-15

    Applicant: Cisco Technology, Inc.

    Inventor： Abhishek Bhat ,  Romesh Kumar Nandwana ,  Pavan Kumar Hanumolu ,  Kadaba Lakshmikumar

    IPC: H03L7/099

    CPC classification number: H03L7/099

    Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.

    LOW AREA EQUALIZER WITH LANE MISMATCH ADAPTATION FOR SUB-RATE RECEIVERS
    8.
    发明公开
    LOW AREA EQUALIZER WITH LANE MISMATCH ADAPTATION FOR SUB-RATE RECEIVERS 审中-公开

    公开(公告)号：US20230155618A1

    公开(公告)日：2023-05-18

    申请号：US17528413

    申请日：2021-11-17

    Applicant: Cisco Technology, Inc.

    Inventor： Romesh Kumar Nandwana ,  Abhishek Bhat ,  Kadaba Lakshmikumar ,  Pavan Kumar Hanumolu

    IPC: H04B1/16 ,  H03M1/66

    CPC classification number: H04B1/16 ,  H03M1/66

    Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

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