公开(公告)号：US11894468B2

公开(公告)日：2024-02-06

申请号：US17291689

申请日：2019-10-30

Applicant: Cornell University

Inventor： Wenshen Li ,  Zongyang Hu ,  Kazuki Nomoto ,  Debdeep Jena ,  Huili Grace Xing

IPC: H01L29/872 ,  H01L29/24 ,  H01L29/36 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/8725 ,  H01L29/24 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66969

Abstract: Described herein are the design and fabrication of Group III trioxides, such as β-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as β-Ga2O3.

公开(公告)号：US20190148584A1

公开(公告)日：2019-05-16

申请号：US16192325

申请日：2018-11-15

Applicant: Cornell University ,  University of Notre Dame du Lac

Inventor： SM Islam ,  Vladimir Protasenko ,  Huili Grace Xing ,  Debdeep Jena ,  Jai Verma

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00

Abstract: A DUV-LED including a bottom substrate, a n-contact/injection layer formed on the bottom substrate, a p-contact region, and an emitting active region between the n-contact/injection layer and the contact region. The emitting active region includes at least one GaN quantum heterostructure. The at least one GaN quantum heterostructures is sized and shaped to determine a certain emission wavelength. Preferably, the certain emission wavelength is in a range of approximately 219-280 nm. In one embodiment, the size is controlled by precisely controlling parameters selected from the group consisting of: an epitaxial deposition time; a Ga/N ratio; a thermal annealing time; a temperature during deposition; and combinations thereof.

公开(公告)号：US12243921B2

公开(公告)日：2025-03-04

申请号：US18209323

申请日：2023-06-13

Applicant: Cornell University

Inventor： Zongyang Hu ,  Kazuki Nomoto ,  Grace Huili Xing ,  Debdeep Jena ,  Wenshen Li

IPC: H01L29/417 ,  C30B29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

公开(公告)号：US11715774B2

公开(公告)日：2023-08-01

申请号：US17042153

申请日：2019-03-28

Applicant: Cornell University

Inventor： Zongyang Hu ,  Kazuki Nomoto ,  Grace Huili Xing ,  Debdeep Jena ,  Wenshen Li

IPC: H01L29/417 ,  C30B29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  C30B29/16 ,  H01L29/66969 ,  H01L29/7827

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

公开(公告)号：US11476383B2

公开(公告)日：2022-10-18

申请号：US16966775

申请日：2019-01-31

Applicant: Cornell University

Inventor： Henryk Turski ,  Debdeep Jena ,  Huili Grace Xing ,  Shyam Bharadwaj ,  Alexander Austin Chaney ,  Kazuki Nomoto

IPC: H01L33/00 ,  H01L33/06 ,  H01S5/22 ,  H01S5/30 ,  H01L33/32 ,  H01L33/12

Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.

公开(公告)号：US20210384362A1

公开(公告)日：2021-12-09

申请号：US17291689

申请日：2019-10-30

Applicant: Cornell University

Inventor： Wenshen Li ,  Zongyang Hu ,  Kazuki Nomoto ,  Debdeep Jena ,  Huili Grace Xing

IPC: H01L29/872 ,  H01L29/24 ,  H01L29/36 ,  H01L29/40 ,  H01L29/66

Abstract: Described herein are the design and fabrication of Group III trioxides, such as β-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the re-quirements unique to Group III trioxides, such as β-Ga2O3.

公开(公告)号：US12051474B2

公开(公告)日：2024-07-30

申请号：US17821789

申请日：2022-08-23

Applicant: Cornell University

Inventor： Amit Lal ,  Shubham Jadhav ,  Ved Gund ,  Benyamin Davaji ,  Grace Xing ,  Debdeep Jena

IPC: G11C23/00

CPC classification number: G11C23/00

Abstract: Disclosed are ferroelectric devices including devices for performing a multiplication of analog input signals and resonators. In one aspect, a ferroelectric nanoelectromechanical device includes a first structural beam, a first input electrode disposed on a first top portion of the first structural beam, and an output electrode. The apparatus further includes a first ferroelectric film disposed on a second top portion of the first input electrode, and a first resistive layer disposed on a third top portion of the first ferroelectric film, wherein a first electrode is positioned at a first end of the first resistive layer and a second electrode is positioned at a second end of the first resistive layer.

公开(公告)号：US20230326984A1

公开(公告)日：2023-10-12

申请号：US18209323

申请日：2023-06-13

Applicant: Cornell University

Inventor： Zongyang Hu ,  Kazuki Nomoto ,  Grace Huili Xing ,  Debdeep Jena ,  Wenshen Li

IPC: H01L29/417 ,  C30B29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  C30B29/16 ,  H01L29/66969 ,  H01L29/7827

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

公开(公告)号：US11522080B2

公开(公告)日：2022-12-06

申请号：US16676083

申请日：2019-11-06

Applicant: Cornell University

Inventor： Samuel James Bader ,  Reet Chaudhuri ,  Huili Grace Xing ,  Debdeep Jena

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

Abstract: III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

公开(公告)号：US20210043795A1

公开(公告)日：2021-02-11

申请号：US16966775

申请日：2019-01-31

Applicant: Cornell University

Inventor： Henryk Turski ,  Debdeep Jena ,  Huili Grace Xing ,  Shyam Bharadwaj ,  Alexander Austin Chaney ,  Kazuki Nomoto

IPC: H01L33/00 ,  H01S5/22 ,  H01L33/06 ,  H01S5/30

Abstract: A device that includes a metal(III)-polar III-nitride substrate having a first surface opposite a second surface, a tunnel junction formed on one of the first surface or a buffer layer disposed on the first surface, a p-type III-nitride layer formed directly on the tunnel junction, and a number of material layers; a first material layer formed on the p-type III-nitride layer, each subsequent layer disposed on a preceding layer, where one layer from the number of material layers is patterned into a structure, that one layer being a III-nitride layer. Methods for forming the device are also disclosed.