公开(公告)号：US5963047A

公开(公告)日：1999-10-05

申请号：US917148

申请日：1997-08-25

Applicant: David Kwong ,  Huijun Jeffrey Cui

Inventor： David Kwong ,  Huijun Jeffrey Cui

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00361

Abstract: A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver transistor. Both transistors drive the output low in parallel initially during a voltage transition, but the larger transistor is disabled for the remainder of the output voltage swing when reflections and ringing occur. A pulse is generated by a transition detector when an input to the output buffer transitions low. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. A Resistor in series with the smaller driver transistor absorbs these reflections. The output impedance is pulsed to the higher impedance of the first stage when ringing occurs at the end of the voltage transition, but after the pulse ends, the lower impedance of the large driver is seen. Pulses are generated when any neighboring output changes. The pulse generated is sent to all neighboring output buffers to disable their large drivers when noise in injected into the power or ground supplies.

Abstract translation: CMOS输出缓冲器具有较小的驱动晶体管和较大驱动晶体管的下拉电阻。 两个晶体管最初在电压转换期间并联驱动输出低电平，但是当出现反射和振铃时，较大的晶体管将被禁止输出电压摆幅的其余部分。 当输出缓冲器的输入变为低电平时，转换检测器产生脉冲。 生成的脉冲会在较短的时间内禁用较大的驱动程序，但稍后重新启用驱动程序。 因此，在开关完成后，大的驱动器保持接通，从而提供大的IOH和IOL静电流。 脉冲长度足以保持大驱动器禁用，同时接收反射并在电压转换后发生振铃。 与较小的驱动晶体管串联的电阻吸收这些反射。 当在电压转换结束时发生振铃时，输出阻抗被脉冲到第一级的较高阻抗，但是在脉冲结束之后，看到大驱动器的阻抗较低。 当任何相邻的输出变化时产生脉冲。 所产生的脉冲被发送到所有相邻的输出缓冲器，以在注入电源或地面的噪声供给时禁用它们的大驱动器。

公开(公告)号：US07068091B1

公开(公告)日：2006-06-27

申请号：US10376056

申请日：2003-02-27

Applicant: David Kwong

Inventor： David Kwong

IPC: H03L5/00

CPC classification number: H03K19/0013 ,  H03K19/018521

Abstract: A circuit for use in conjunction with a portion of a core of an integrated circuit, for shifting a signal from a first voltage level to a second voltage level, wherein the circuit is formed using the same process type transistors (i.e., low voltage transistors) as are used in the core of the integrated circuit.

Abstract translation: 一种与集成电路的核心部分结合使用的电路，用于将信号从第一电压电平转换到第二电压电平，其中电路使用相同的处理型晶体管（即，低电压晶体管）形成， 如在集成电路的核心中使用的那样。

公开(公告)号：US06757147B1

公开(公告)日：2004-06-29

申请号：US10063622

申请日：2002-05-03

Applicant: Paul C. F. Tong ,  David Kwong ,  Ping Ping Xu

Inventor： Paul C. F. Tong ,  David Kwong ,  Ping Ping Xu

IPC: H02H322

CPC classification number: H02H9/046 ,  H01L27/0251

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract translation: 交叉引脚静电放电（ESD）保护器件可防止两个I / O引脚之间的ESD陷阱。 引脚A连接到总线开关晶体管的漏极，引脚B连接到晶体管的源极。 引脚A上的ESD保护器件具有内部接地总线的n沟道分流晶体管。 分流晶体管的栅极是与栅极A电容耦合的交叉栅极节点，并具有接地的漏电阻。 n沟道交叉接地晶体管的栅极连接到同一个交叉栅极节点，但它将内部接地总线连接到引脚B，引脚B在引脚到引脚ESD测试中接地。 引脚A上的ESD脉冲驱动交叉栅极节点为高电平，导通分流晶体管和交叉接地晶体管。 浮地内部接地总线通过引脚B连接到地，将总线开关晶体管的基板接地，以防止其导通。

公开(公告)号：US06552583B1

公开(公告)日：2003-04-22

申请号：US09682734

申请日：2001-10-11

Applicant: David Kwong

Inventor： David Kwong

IPC: H02H904

CPC classification number: H01L27/0285

Abstract: Large output driver transistors are used to shunt electro-static-discharge (ESD) pulses. ESD pulses are capacitivly coupled to the gates of the large driver transistors by R-C networks. The capacitive coupling causes a gate-to-source voltage to exceed the transistor threshold, turning on the large driver transistor to shunt the ESD current. Transistor switches are inserted into the R-C networks. These transistor switches disconnect the R-C networks during normal operation, and ensure that the R-C networks couple the I/O pad to the gates of the output driver transistors only when power is turned off. Since ESD events normally occur when power is disconnected, such as during handling by a person or machine, the ESD protection is only needed when power is off. Thus an active ESD-protection device can be disabled during normal powered operation of the IC. A feedback circuit detects power and biases the gates of the transistor switches.

Abstract translation: 大输出驱动晶体管用于分流静电放电（ESD）脉冲。 ESD脉冲通过R-C网络电容耦合到大驱动器晶体管的栅极。 电容耦合导致栅极至源极电压超过晶体管阈值，导通大驱动晶体管以分流ESD电流。 晶体管开关插入到R-C网络中。 这些晶体管开关在正常操作期间断开R-C网络，并确保只有在电源关闭时，R-C网络将I / O焊盘耦合到输出驱动器晶体管的栅极。 由于ESD事件通常在电源断开时发生，例如在人员或机器处理过程中，ESD保护仅在电源关闭时才需要。 因此，在IC的正常供电操作期间，可以禁用有源ESD保护器件。 反馈电路检测功率并偏置晶体管开关的栅极。

公开(公告)号：US06542031B2

公开(公告)日：2003-04-01

申请号：US09683195

申请日：2001-11-29

Applicant: David Kwong

Inventor： David Kwong

IPC: H03F345

CPC classification number: H03K19/0016 ,  H03K19/018528 ,  H03K19/1738

Abstract: A differential buffer/driver has a switch network that connects an IOH current source to a differential output to be drive high, and connects an IOL current source to the other differential output to be driven low. Each output can be connected to a pull-down boost current sink. A boost pulse momentarily connects a boost current sink to the differential output being driven low. The differential buffer generates a pair of boost pulses to activate the boost current for either differential output. One boost pulse is activated when one differential output is driven low, while the other boost pulse is activated when the other differential output is driven low.

Abstract translation: 差分缓冲器/驱动器具有将IOH电流源连接到差分输出以将其驱动为高电平的开关网络，并将IOL电流源连接到另一个差分输出以被驱动为低电平。 每个输出可以连接到下拉升压电流接收器。 升压脉冲瞬间将升压电流接收器连接到差分输出端被驱动为低电平。 差分缓冲器产生一对升压脉冲以激活用于差分输出的升压电流。 当一个差分输出驱动为低电平时，一个升压脉冲被激活，而另一个升压脉冲在另一个差分输出被驱动为低电平时被激活。

公开(公告)号：US06366124B1

公开(公告)日：2002-04-02

申请号：US09681651

申请日：2001-05-16

Applicant: David Kwong

Inventor： David Kwong

IPC: H03K190175

CPC classification number: H03K19/01855 ,  H03K3/356113 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693

Abstract: A voltage translator programmably converts signals generated from a first power-supply voltage to a second power-supply voltage, or vice-versa. In response to control signals, bootstrap switches connect either the first or second power supply to a first internal supply, and either the second or first power supply to a second internal supply. A pair of inverters are sourced by the first power supply and generate true and complement data signals. Cross-coupled p-channel load transistors are sourced by the second internal power supply. A differential pair of n-channel transistors have drains connected to the drains of the load transistors, and gates driven by the true and complement data signals. The bootstrap switches use boosted signals above the power-supply voltages to programmably connect full-voltage power supplies to the internal supplies.

Abstract translation: 电压转换器可编程地将从第一电源电压产生的信号转换为第二电源电压，反之亦然。 响应于控制信号，自举开关将第一或第二电源连接到第一内部电源，将第二或第一电源连接到第二内部电源。 一对逆变器由第一个电源提供，并产生真实和补充数据信号。 交叉耦合的p沟道负载晶体管由第二个内部电源供电。 n沟道晶体管的差分对具有连接到负载晶体管的漏极的漏极和由真实和补充数据信号驱动的栅极。 自举开关使用高于电源电压的升压信号可编程地将全电压电源连接到内部电源。

公开(公告)号：US06335638B1

公开(公告)日：2002-01-01

申请号：US09607558

申请日：2000-06-29

Applicant: David Kwong ,  Kwong Shing Lin

Inventor： David Kwong ,  Kwong Shing Lin

IPC: G06F104

CPC classification number: G06F1/10 ,  H03K4/00 ,  H03K17/164

Abstract: A clock driver for an integrated circuit reduces electro-magnetic interference (EMI) induced in nearby metal traces yet also reduces jitter due to noise at the switching threshold. A weak driver using small n-channel and p-channel transistors initially drives the clock line. Then a pulse generator produces a short pulse to a gate of a large driver transistor. The large driver transistor is pulsed on for a very short period of time. The large driver transistor is turned off by the end of the pulse before the clock line completes its transition. The weak driver then finishes the clock-line transition. Since only the weak driver is on during the start and end of the transition, a slow voltage-slew rate occurs at the beginning and end of the transition. The large driver transistor is on only in the middle of the transition, producing a fast voltage-slew rate in the middle. A triple-slope waveform results. Since a fast voltage-slew occurs in the middle of the transition near the receiver's switching threshold, clock jitter due to supply noise is reduced. EMI is reduced because the average slew rate is reduced.

Abstract translation: 用于集成电路的时钟驱动器可减少在附近的金属走线中引起的电磁干扰（EMI），同时还可减少由于切换阈值引起的噪声引起的抖动。 使用小n沟道和p沟道晶体管的弱驱动器最初驱动时钟线。 然后，脉冲发生器产生对大驱动晶体管的栅极的短脉冲。 大的驱动晶体管在非常短的时间内被脉冲通电。 在时钟线完成转换之前，大的驱动晶体管由脉冲结束而关闭。 然后弱驱动器完成时钟线转换。 由于在转换开始和结束时只有弱驱动器导通，所以在转换开始和结束时会产生缓慢的电压转换速率。 大型驱动晶体管只在转换中间，在中间产生快速的电压转换速率。 产生三斜坡波形。 由于在靠近接收器切换阈值的转换中间发生快速电压转换，因此降低了由于电源噪声引起的时钟抖动。 平均压摆率降低导致EMI降低。

公开(公告)号：US07327199B1

公开(公告)日：2008-02-05

申请号：US11233963

申请日：2005-09-23

Applicant: David Kwong ,  Trung Tran

Inventor： David Kwong ,  Trung Tran

IPC: G01R35/00

CPC classification number: G01R31/31727 ,  G01R31/31701 ,  H03L7/0891 ,  H03L7/095

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract translation: 根据一个实施例，锁相环（PLL）装置包括用于在PLL的参考时钟输入端接收到特定脉冲串时进入/退出测试模式的测试电路。 此外，本文提供了用于输入测试模式和检测PLL内的环路滤波器泄漏的示例性方法。 在不使用专用测试针的情况下执行本文描述的方法。

公开(公告)号：US06738242B1

公开(公告)日：2004-05-18

申请号：US09683968

申请日：2002-03-07

Applicant: David Kwong ,  Paul C. F. Tong

Inventor： David Kwong ,  Paul C. F. Tong

IPC: H02H900

CPC classification number: H02H9/046

Abstract: A bus-switch transistor connects two I/O pins when an enable signal on its gate is activated. Each pin has an electro-static-discharge (ESD) protection devices. When the internal ground and the enable are floating, and an ESD pulse is applied between the two pins, an isolation circuit couples part of the ESD pulse to the gate of the bus-switch transistor, keeping the transistor turned off. This forces the ESD pulse to travel through the ESD protection devices, preventing damage to the bus-switch transistor. The isolation circuit has a capacitor between a pin and the gate of a coupling transistor. The capacitor couples the ESD pulse to the gate of the coupling transistor. The coupling transistor turns on, connecting the pin to the gate of a grounding transistor. The grounding transistor then turns on, connecting the gate of the bus-switch transistor to the other pin, which is grounded during the ESD test.

Abstract translation: 总线开关晶体管在其门上的使能信号被激活时连接两个I / O引脚。 每个引脚都有一个静电放电（ESD）保护装置。 当内部接地和使能浮动，并且两个引脚之间施加ESD脉冲时，隔离电路将ESD脉冲的一部分耦合到总线开关晶体管的栅极，从而保持晶体管截止。 这将强制ESD脉冲穿过ESD保护器件，防止损坏总线开关晶体管。 隔离电路在引脚和耦合晶体管的栅极之间具有电容器。 电容器将ESD脉冲耦合到耦合晶体管的栅极。 耦合晶体管导通，将引脚连接到接地晶体管的栅极。 然后接地晶体管导通，将总线开关晶体管的栅极连接到在ESD测试期间接地的另一个引脚。

公开(公告)号：US06559703B1

公开(公告)日：2003-05-06

申请号：US09607460

申请日：2000-06-29

Applicant: David Kwong ,  Eddie Siu Yam Chan

Inventor： David Kwong ,  Eddie Siu Yam Chan

IPC: H03K190175

CPC classification number: H03K17/165

Abstract: A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a sense-pulse circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off. An external direction signal may also be used to pre-activate the connecting transistor for one of the two sides of the bus switch transistor, replacing the sense-pulse circuits.

Abstract translation: 一个总线开关可以防止其任何一个端子的下冲。 总线开关晶体管是n沟道金属氧化物半导体（MOS），其源极连接到第一总线，其漏极连接到第二总线。 在隔离期间，总线开关晶体管的栅极节点由脉冲晶体管放电到地，然后由漏电晶体管保持接地。 感测脉冲电路连接到第一和第二总线。 当由感测脉冲电路检测到低电平转换时，n沟道连接晶体管导通，通过接地栅极n沟道晶体管将总线与低电平跃迁连接到栅极节点。 如果发生下冲，则耦合到门节点。 由于总线开关晶体管的栅极和源极都耦合到下冲，栅极至源极电压不会达到晶体管阈值，并且总线开关晶体管保持关断。 也可以使用外部方向信号来预先激活用于总线开关晶体管的两侧之一的连接晶体管，代替感测脉冲电路。