公开(公告)号：US20240196531A1

公开(公告)日：2024-06-13

申请号：US18586336

申请日：2024-02-23

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/11 ,  A61B5/00 ,  A61B5/145 ,  A61B5/1468 ,  G01N27/327 ,  H01L21/768 ,  H01L23/48 ,  H05K1/02 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/112 ,  A61B5/6802 ,  H01L21/768 ,  H01L23/481 ,  H05K1/0262 ,  H05K3/403 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/1468 ,  A61B5/6848 ,  G01N27/327 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/0394 ,  H05K2201/049 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/09181 ,  H05K2201/10151 ,  H05K2201/10378

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US12250768B2

公开(公告)日：2025-03-11

申请号：US18381074

申请日：2023-10-17

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/02 ,  A61B5/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66 ,  H03B5/32 ,  H05K1/11 ,  H05K3/40 ,  A61B5/145 ,  A61B5/1468 ,  G01N27/327 ,  H05K1/14

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US11950363B2

公开(公告)日：2024-04-02

申请号：US17542977

申请日：2021-12-06

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/09 ,  A61B5/00 ,  A61B5/1468 ,  A61B5/1495 ,  A61B5/24 ,  H01L21/768 ,  H01L21/78 ,  H01L23/36 ,  H01L23/48 ,  H01L23/50 ,  H01L23/552 ,  H05K1/02 ,  H05K1/11 ,  H05K3/02 ,  H05K3/40 ,  A61B5/145 ,  G01N27/327 ,  H05K1/14

CPC classification number: H05K1/112 ,  A61B5/6802 ,  H01L21/768 ,  H01L23/481 ,  H05K1/0262 ,  H05K3/403 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/1468 ,  A61B5/6848 ,  G01N27/327 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/0394 ,  H05K2201/049 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/09181 ,  H05K2201/10151 ,  H05K2201/10378

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US20240049388A1

公开(公告)日：2024-02-08

申请号：US18381074

申请日：2023-10-17

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/11 ,  A61B5/00 ,  H01L21/768 ,  H01L23/48 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/112 ,  A61B5/6802 ,  H01L21/768 ,  H01L23/481 ,  H05K1/0262 ,  H05K3/403 ,  H05K2201/10151 ,  H05K2201/09181 ,  H05K2201/10378 ,  H05K2201/09063 ,  A61B5/1468

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US20220095454A1

公开(公告)日：2022-03-24

申请号：US17542977

申请日：2021-12-06

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/11 ,  A61B5/00 ,  H01L21/768 ,  H01L23/48 ,  H05K1/02 ,  H05K3/40 ,  A61B5/24

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US10660201B2

公开(公告)日：2020-05-19

申请号：US16282587

申请日：2019-02-22

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K3/40 ,  A61B5/04 ,  A61B5/00 ,  H01L21/768 ,  H01L23/48 ,  A61B5/1468 ,  A61B5/145 ,  G01N27/327

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US11224125B2

公开(公告)日：2022-01-11

申请号：US16850986

申请日：2020-04-16

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  H01L21/02 ,  H01L21/48 ,  H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  A61B5/00 ,  H01L21/768 ,  A61B5/24 ,  A61B5/1468 ,  A61B5/145 ,  G01N27/327

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US20200245459A1

公开(公告)日：2020-07-30

申请号：US16850986

申请日：2020-04-16

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/11 ,  A61B5/04 ,  A61B5/00 ,  H01L21/768 ,  H01L23/48 ,  H05K1/02 ,  H05K3/40

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.