公开(公告)号：US08841708B2

公开(公告)日：2014-09-23

申请号：US13468332

申请日：2012-05-10

Applicant: Donald R. Disney ,  Richard J. Brown ,  Hui Nie

Inventor： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

IPC: H01L29/808

CPC classification number: H01L29/41741 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66446 ,  H01L29/8083

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract translation: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。 沟道结构包括第一III族氮化物外延材料，其特征在于一个或多个沟道侧壁。 半导体器件还包括耦合到沟道结构的源极区域。 源区包括第二III族氮化物外延材料。 所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构，与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。 电介质层的顶表面与源区的顶表面基本上共面。

公开(公告)号：US08698164B2

公开(公告)日：2014-04-15

申请号：US13315720

申请日：2011-12-09

Applicant: Donald R. Disney ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown

Inventor： Donald R. Disney ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown

IPC: H01L29/808 ,  H01L21/335

CPC classification number: H01L29/8083 ,  H01L29/0623 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/66909 ,  H01L29/66924

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract translation: 半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 第一电极电耦合到GaN衬底的第二表面。 半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。 第一GaN外延层包括沟道区。 第二GaN外延层包括栅极区域和边缘端接结构。 耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

公开(公告)号：US08513087B2

公开(公告)日：2013-08-20

申请号：US13095019

申请日：2011-04-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/76

CPC classification number: H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20130032895A1

公开(公告)日：2013-02-07

申请号：US13195199

申请日：2011-08-01

Applicant: Donald R. Disney ,  Ognjen Milic ,  Kun Yi

Inventor： Donald R. Disney ,  Ognjen Milic ,  Kun Yi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66659

Abstract: A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

Abstract translation: 高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋电阻场板通过第一隔离与第一阱区域分离 并且耦合在漏极区域和源极区域之间。 高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离 并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

公开(公告)号：US20120314453A1

公开(公告)日：2012-12-13

申请号：US13571209

申请日：2012-08-09

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L27/088 ,  H02M3/335

CPC classification number: H01L29/7803 ,  G05F1/14 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7802 ,  H01L29/7813 ,  H02M1/36 ,  H02M3/335 ,  H02M3/33507 ,  H02M3/33553 ,  H02M3/33561 ,  H02M2001/0009

Abstract: An example control element for use in a power supply includes a high-voltage transistor and a control circuit to control switching of the high-voltage transistor. The high-voltage transistor includes a drain region, source region, tap region, drift region, and tap drift region, all of a first conductivity type. The transistor also includes a body region of a second conductivity type. An insulated gate is included in the transistor such that when the insulated gate is biased a channel is formed across the body region to form a conduction path between the source region and the drift region. A voltage at the tap region with respect to the source region is substantially constant and less than a voltage at the drain region with respect to the source region in response to the voltage at the drain region exceeding a pinch off voltage.

Abstract translation: 用于电源的示例性控制元件包括高压晶体管和用于控制高压晶体管的开关的控制电路。 高压晶体管包括漏区，源区，抽头区，漂移区和抽头漂移区，全部为第一导电类型。 晶体管还包括第二导电类型的体区。 绝缘栅极包括在晶体管中，使得当绝缘栅极被偏置时，跨越体区域形成沟道以在源极区域和漂移区域之间形成传导路径。 相对于源极区域的抽头区域处的电压基本上是恒定的，并且响应于漏极区域处的电压超过夹断电压而小于相对于源极区域的漏极区域处的电压。

公开(公告)号：US20110084333A1

公开(公告)日：2011-04-14

申请号：US12576150

申请日：2009-10-08

Applicant: Donald R. Disney ,  Michael R. Hsing

Inventor： Donald R. Disney ,  Michael R. Hsing

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/2254 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66712

Abstract: Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.

Abstract translation: 本文公开了具有超连接和相关制造方法的功率器件。 在一个实施例中，形成功率器件的方法包括在衬底材料上形成外延层并在外延层中形成沟槽。 沟槽具有第一侧壁，第二侧壁和位于第一和第二侧壁之间的底部。 该方法还包括在沟槽的第一和第二侧壁中的至少一个上形成绝缘材料，并且经由绝缘材料经由沟槽的第一和第二侧壁中的至少一个将掺杂剂扩散到外延层中。

公开(公告)号：US20110062489A1

公开(公告)日：2011-03-17

申请号：US12557841

申请日：2009-09-11

Applicant: Donald R. Disney ,  Ognjen Milic

Inventor： Donald R. Disney ,  Ognjen Milic

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/82

CPC classification number: H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66333 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7395

Abstract: An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch.

Abstract translation: 公开了一种具有自对准硅化物的改进的功率器件及其制造方法。 示例性功率器件是垂直功率器件，其包括通过至少基本上自对准的硅化（例如自对准硅）工艺在栅极和体接触区域上形成的触点。 示例性装置还可以包括一个或多个侧壁间隔件，每个侧壁间隔件至少基本上对准在栅极区域和主体接触区域的边缘之间。 身体接触区域也可以以至少基本上与对侧隔离物自对准的方式植入到装置中。 该方法还可以包括至少基本上自对准的硅蚀刻。

公开(公告)号：US07872304B2

公开(公告)日：2011-01-18

申请号：US12688778

申请日：2010-01-15

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H01L21/8222

CPC classification number: H02M1/36 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/808 ,  H02M3/33507 ,  H03K17/0822

Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中，电路包括设置在具有第一，第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时，设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例， 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时，在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。

公开(公告)号：US20100133611A1

公开(公告)日：2010-06-03

申请号：US12658020

申请日：2010-02-01

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

Abstract translation: 晶体管形成在隔离结构内，该隔离结构包括底板隔离区域和从衬底表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。

公开(公告)号：US20100117718A1

公开(公告)日：2010-05-13

申请号：US12688778

申请日：2010-01-15

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H03K3/01

CPC classification number: H02M1/36 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/808 ,  H02M3/33507 ,  H03K17/0822

Abstract: A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage provided at a third terminal of the first transistor is substantially proportional to a voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is less than a pinch-off voltage of the first transistor. The voltage provided at the third terminal of the first transistor is substantially constant and less than the voltage between the first and second terminals of the first transistor when the voltage between the first and second terminals of the first transistor is greater than the pinch-off voltage of the first transistor. The circuit also includes a control circuit disposed in the first substrate and coupled to the third terminal of the first transistor. The circuit further includes a second transistor disposed in a second substrate. A first terminal of the second transistor coupled to the external voltage.

Abstract translation: 具有高电压检测装置的控制电路。 在一个实施例中，电路包括设置在具有第一，第二和第三端子的第一基板中的第一晶体管。 第一晶体管的第一端子耦合到外部电压。 当第一晶体管的第一和第二端子之间的电压小于第一晶体管的钳位电压时，设置在第一晶体管的第三端处的电压基本上与第一晶体管的第一和第二端子之间的电压成比例， 第一晶体管。 当第一晶体管的第一端和第二端之间的电压大于夹断电压时，在第一晶体管的第三端处提供的电压基本上恒定且小于第一晶体管的第一和第二端之间的电压 的第一晶体管。 电路还包括设置在第一基板中并耦合到第一晶体管的第三端子的控制电路。 电路还包括设置在第二基板中的第二晶体管。 第二晶体管的第一端子耦合到外部电压。