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    Reduced overhead gate level logic encryption
    1.
    发明授权
    Reduced overhead gate level logic encryption 有权

    公开(公告)号：US11282414B2

    公开(公告)日：2022-03-22

    申请号：US15770380

    申请日：2016-10-24

    Applicant: Drexel University ,  Ioannis Savidis ,  Kyle Juretus

    Inventor： Ioannis Savidis ,  Kyle Juretus

    IPC: H04L29/00 ,  G09C1/04 ,  G09C1/00 ,  G06F30/39 ,  G06F21/72 ,  H04L9/08

    Abstract: There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.

    Protecting analog circuits with parameter biasing obfuscation
    2.
    发明授权
    Protecting analog circuits with parameter biasing obfuscation 有权

    公开(公告)号：US10923442B2

    公开(公告)日：2021-02-16

    申请号：US15918278

    申请日：2018-03-12

    Applicant: Drexel University

    Inventor： Ioannis Savidis ,  Vaibhav Venugopal Rao ,  Kyle Juretus

    IPC: H01L23/00 ,  G09C1/00 ,  H03L7/089 ,  H03B5/12 ,  H03L7/091 ,  H04L9/32 ,  H04L9/08 ,  H03L7/085 ,  H03B7/06

    Abstract: A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.

    Reducing logic locking key leakage through the scan chain
    3.
    发明授权
    Reducing logic locking key leakage through the scan chain 有权

    公开(公告)号：US11971987B2

    公开(公告)日：2024-04-30

    申请号：US17480771

    申请日：2021-09-21

    Applicant: Drexel University

    Inventor： Kyle Joseph Juretus ,  Ioannis Savidis

    IPC: G06F21/55 ,  G06F21/76

    CPC classification number: G06F21/556 ,  G06F21/76 ,  G06F2221/034

    Abstract: A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

    RECONFIGURABLE ARRAY FOR ANALOG APPLICATIONS
    4.
    发明公开
    RECONFIGURABLE ARRAY FOR ANALOG APPLICATIONS 审中-公开

    公开(公告)号：US20230344431A1

    公开(公告)日：2023-10-26

    申请号：US18184692

    申请日：2023-03-16

    Applicant: Drexel University

    Inventor： Ioannis Savidis ,  Ziyi Chen

    IPC: H03K19/17704 ,  H03K19/17736 ,  H03K19/17732

    CPC classification number: H03K19/17712 ,  H03K19/1774 ,  H03K19/17732

    Abstract: A field-programmable analog array (FPAA) fabric includes a 6×6 matrix of configurable analog blocks (CABs). The implementation of programmable CABs eliminates the use of fixed analog subcircuits. A unique routing strategy is developed within the CAB units that supports both differential and single-ended mode circuit configurations. The bandwidth limitation due to the routing switches of each individual CAB unit is compensated for through the use of a switch-less routing network between CABs. Algorithms and methodologies facilitate rapid implementation of analog circuits on the FPAA. The proposed FPAA fabric provides high operating speeds as compared to existing FPAA topologies, while providing greater configuration in the CAB units as compared to switch-less FPAA. The FPAA core includes 498 programming switches and 14 global switchless interconnects, while occupying an area of 0.1 mm2 in a 65 nm CMOS process.

    Transistor sizing for parameter obfuscation of analog circuits
    7.
    发明授权
    Transistor sizing for parameter obfuscation of analog circuits 有权

    公开(公告)号：US11157674B2

    公开(公告)日：2021-10-26

    申请号：US16778550

    申请日：2020-01-31

    Applicant: Drexel University

    Inventor： Vaibhav Venugopal Rao ,  Ioannis Savidis

    IPC: G06F30/373 ,  G06F30/327 ,  H01L23/00

    Abstract: An approach is described for enhancing the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements.

    Charge recycling from idle circuits for improved energy efficiency of multi-voltage systems
    8.
    发明授权
    Charge recycling from idle circuits for improved energy efficiency of multi-voltage systems 有权

    公开(公告)号：US11641200B2

    公开(公告)日：2023-05-02

    申请号：US17307118

    申请日：2021-05-04

    Applicant: Drexel University

    Inventor： Md Shazzad Hossain ,  Ioannis Savidis

    IPC: H03K17/16 ,  G06F1/3234 ,  H03K19/00 ,  G06F1/3296

    Abstract: A method for the delivery of power to subthreshold (sub-Vt) circuits uses unused current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Algorithmic and circuit techniques use dynamic management of idle cores when reusing the leakage current of the idle cores. A scheduling algorithm, longest idle time-leakage reuse (LIT-LR) enables energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the switch and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a usage ranking based algorithm, longest idle time-simultaneous leakage reuse and power gating (LIT-LRPG) enables simultaneous implementation of power gating (PG) and leakage reuse in a multiprocessor system-on-chip (MPSoC) platform.

    REDUCING LOGIC LOCKING KEY LEAKAGE THROUGH THE SCAN CHAIN
    9.
    发明申请
    REDUCING LOGIC LOCKING KEY LEAKAGE THROUGH THE SCAN CHAIN 有权

    公开(公告)号：US20230090772A1

    公开(公告)日：2023-03-23

    申请号：US17480771

    申请日：2021-09-21

    Applicant: Drexel University

    Inventor： Kyle Joseph Juretus ,  Ioannis Savidis

    IPC: G06F21/55 ,  H03K19/20

    Abstract: A proposed technique allows for the security of the logic cone through logic locking and secures the outputs of the circuit from the scan chain without modifications to the structure of the scan chain. Since the oracle responses in test mode do not correspond to the functional key, satisfiability (SAT) attacks are not able to leverage the responses from the scan chain. In addition, a charge accumulation circuit is developed to prevent and detect any attempt to enter the partitioned test mode while the correct circuit responses are still stored within the registers.

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