公开(公告)号：US10466572B2

公开(公告)日：2019-11-05

申请号：US15679879

申请日：2017-08-17

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: G02F1/35 ,  G02F1/39 ,  H03H9/56 ,  H03H9/02 ,  H03H3/02 ,  H01S3/00 ,  H03B17/00

Abstract: 1. A method of fabricating an RF filter comprising an array of resonators comprising the steps of: Obtaining a removable carrier with release layer; Growing a piezoelectric film on a removable carrier; Applying a first electrode to the piezoelectric film; Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; Attaching the backing membrane to the first electrode; Detaching the removable carrier; Measuring and trimming the piezoelectric film as necessary; Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; Etching down through coatings and backing membrane to a silicon dioxide layer between the backing membrane and the cover to form trenches; Applying a passivation layer into the trenches and around the piezoelectric islands; Depositing a second electrode layer over the piezoelectric film islands and surrounding passivation layer; Applying connections for subsequent electrical coupling to an interposer; Selectively removing second electrode material leaving coupled resonator arrays; Creating a gasket around perimeter of the resonator array; Thinning down cover to desired thickness; Optionally fabricating upper cavities between the backing membrane and cover by drilling holes through the cover and then selectively etching away the silicon dioxide; Dicing the wafer into flip chip single unit filter arrays; Obtaining an interposer; Optionally applying a dam to the interposer surface to halt overfill flow; Coupling the flip chip single unit filter array to pads of the interposer by reflow of the solder cap; Encapsulating with polymer underfill/overfill; and Singulating into separate filter modules, wherein wherein the piezoelectric layer comprises a mixed AlN single crystal layer a c-axis orientation.

公开(公告)号：US20180275485A1

公开(公告)日：2018-09-27

申请号：US15679879

申请日：2017-08-17

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: G02F1/35 ,  G02F1/39 ,  H03H9/56 ,  H03H9/02 ,  H03H3/02 ,  H01S3/00 ,  H03B17/00

CPC classification number: G02F1/353 ,  G02F1/39 ,  H01S3/0092 ,  H03B17/00 ,  H03H3/02 ,  H03H9/02118 ,  H03H9/02228 ,  H03H9/0523 ,  H03H9/1014 ,  H03H9/562 ,  H03H9/587 ,  H03H9/588 ,  H03H9/605 ,  H03H2003/021 ,  H03H2003/023 ,  H04B2210/006

Abstract: 1. A method of fabricating an RF filter comprising an array of resonators comprising the steps of: Obtaining a removable carrier with release layer; Growing a piezoelectric film on a removable carrier; Applying a first electrode to the piezoelectric film; Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; Attaching the backing membrane to the first electrode; Detaching the removable carrier; Measuring and trimming the piezoelectric film as necessary; Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; Etching down through coatings and backing membrane to a silicon dioxide layer between the backing membrane and the cover to form trenches; Applying a passivation layer into the trenches and around the piezoelectric islands; Depositing a second electrode layer over the piezoelectric film islands and surrounding passivation layer; Applying connections for subsequent electrical coupling to an interposer; Selectively removing second electrode material leaving coupled resonator arrays; Creating a gasket around perimeter of the resonator array; Thinning down cover to desired thickness; Optionally fabricating upper cavities between the backing membrane and cover by drilling holes through the cover and then selectively etching away the silicon dioxide; Dicing the wafer into flip chip single unit filter arrays; Obtaining an interposer; Optionally applying a dam to the interposer surface to halt overfill flow; Coupling the flip chip single unit filter array to pads of the interposer by reflow of the solder cap; Encapsulating with polymer underfill/overfill; and Singulating into separate filter modules, wherein wherein the piezoelectric layer comprises a mixed AlN single crystal layer a c-axis orientation.

公开(公告)号：US08816218B2

公开(公告)日：2014-08-26

申请号：US13482074

申请日：2012-05-29

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: H05K1/11 ,  H05K3/46

CPC classification number: H05K1/11 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/46 ,  Y10T156/10 ,  H01L2924/00

Abstract: A multilayer composite electronic structure comprising at least two feature layers extending in an X-Y plane and separated by a via layer comprising a dielectric material that is sandwiched between two adjacent feature layers, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, wherein a first via has different dimensions in the X-Y plane from a second via in the via layer.

Abstract translation: 一种多层复合电子结构，包括至少两个特征层，所述特征层在XY平面中延伸并且由包含夹在两个相邻特征层之间的电介质材料的通孔层隔开，所述通孔层包括通孔，所述通孔在Z方向上连接相邻的特征层 垂直于XY平面，其中第一通孔在XY平面中具有与通孔层中的第二通孔不同的尺寸。

公开(公告)号：US20130333934A1

公开(公告)日：2013-12-19

申请号：US13523116

申请日：2012-06-14

Applicant: Dror Hurwitz ,  Simon Chan ,  Alex Huang

Inventor： Dror Hurwitz ,  Simon Chan ,  Alex Huang

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/4697 ,  H01L21/4857 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/308 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A multilayer electronic structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein at least one multilayered hole crosses at least two layers of the plurality of layers and comprises at least two hole layers in adjacent layers of the multilayer composite electronic structure, wherein the at least two holes in adjacent layers have different dimensions in the X-Y plane, such that a perimeter of the multilayered hole is stepped and where at least one hole is an aperture to a surface of the multilayer electronic structure.

Abstract translation: 一种多层电子结构，包括在XY平面中延伸的多个层，所述多个层由围绕金属通孔的介电材料构成，所述介电材料围绕垂直于所述XY平面的Z方向传导，其中至少一个多层孔穿过所述多个 层，并且在多层复合电子结构的相邻层中包括至少两个孔层，其中相邻层中的至少两个孔在XY平面中具有不同的尺寸，使得多层孔的周边是阶梯状的，并且其中至少一个 孔是多层电子结构的表面的孔。

公开(公告)号：US20070082501A1

公开(公告)日：2007-04-12

申请号：US11250421

申请日：2005-10-17

Applicant: Dror Hurwitz ,  Mardechay Farkash ,  Eva Igner ,  Amit Zeidler ,  Boris Statnikov ,  Benny Michaeli

Inventor： Dror Hurwitz ,  Mardechay Farkash ,  Eva Igner ,  Amit Zeidler ,  Boris Statnikov ,  Benny Michaeli

IPC: H01L21/31 ,  H01L21/331 ,  H01L21/8222 ,  H01L31/00 ,  H01L29/739 ,  H01L21/469

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/108 ,  H05K3/205 ,  H05K3/388 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/0384 ,  H05K2203/0733 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.

Abstract translation: 一种制造电子基板的方法，包括以下步骤： （A）选择第一基层; （B）在所述第一基底层上沉积第一耐蚀刻阻挡层; （C）建立交替导电层和绝缘层的前半层叠层，所述导电层通过绝缘层互连， （D）将第二基层施加到所述第一半叠层上; （F）将光致抗蚀剂的保护涂层施加到第二基层; （F）蚀刻掉第一基层; （G）去除光致抗蚀剂的保护涂层; （H）去除第一耐蚀刻阻挡层; （I）构建交替导电层和绝缘层的第二半叠层，所述导电层通过绝缘层互连，其中所述第二半堆叠具有基本对称的层叠到所述第一半堆叠; （J）将绝缘层施加到交替导电层和绝缘层的第二霍尔堆叠上，（K）去除第二基层，和（L）通过暴露堆叠的外表面上的通孔的端部并施加端接 到此。

公开(公告)号：US5946600A

公开(公告)日：1999-08-31

申请号：US835514

申请日：1997-04-08

Applicant: Dror Hurwitz ,  Eva Igner ,  Boris Yofis ,  Dror Katz

Inventor： Dror Hurwitz ,  Eva Igner ,  Boris Yofis ,  Dror Katz

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H05K3/46 ,  H01L21/44

CPC classification number: H05K3/4647 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K2203/0315 ,  H05K2203/1142

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Abstract translation: 一种用于制造电子互连结构的方法，该方法包括以下步骤：在具有至少一个暴露的铝表面的电介质材料表面上沉积粘附金属层; 在所述粘附金属层上沉积阻挡金属层; 在阻挡金属层上沉积第一层铝; 在第一层铝上沉积中间阻挡金属层; 在中间阻挡金属层的顶部上施加光致抗蚀剂层; 曝光和显影光致抗蚀剂层; 去除暴露的阻挡金属和光致抗蚀剂层，在铝层上留下一层阻挡金属; 通过多孔阳极氧化将未被阻挡金属覆盖的铝层的那些部分转化成多孔氧化铝; 去除多孔氧化铝; 并且去除暴露的阻挡金属和粘合金属层以留下暴露的图案化铝，以及通过该方法制造的电子互连结构。

公开(公告)号：US10439580B2

公开(公告)日：2019-10-08

申请号：US15468766

申请日：2017-03-24

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: H03H3/02 ,  H03H9/10 ,  H03H9/58

Abstract: A method of fabricating an RF filter comprising an array of resonators, the method comprising the steps of: (a) Obtaining a removable carrier with release layer; (b) Growing a piezoelectric film on a removable carrier; (c) Applying a first electrode to the piezoelectric film; (d) Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; (e) Attaching the backing membrane to the first electrode; (f) Detaching the removable carrier; (g) Measuring and trimming the piezoelectric film as necessary; (h) Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; (i) Etching down through coatings backing membrane, silicon dioxide and into silicon handle to form trenches; (j) Applying passivation layer into the trenches and around the piezoelectric islands; (k) Depositing a second electrode layer over the dielectric and piezoelectric film islands; (l) Applying connections for subsequent electrical coupling to an interposer; (m) Selectively remove second electrode material leaving coupled resonator arrays; (n) Create gasket around perimeter of the resonator array; (o) Thinning down cover of handle to desired thickness; (p) Optionally fabricating cavities between the silicon membrane and handle; (q) Dicing the wafer into flip chip single unit filter arrays; (r) Obtaining an interposer; (s) Optionally applying a dam to the interposer surface to halt overfill flow; (t) Coupling the flip chip single unit filter array to pads of the interposer by reflow of the solder cap; (u) Encapsulating with polymer overfill; and (v) Singulating into separate filter modules.

公开(公告)号：US07682972B2

公开(公告)日：2010-03-23

申请号：US11421600

申请日：2006-06-01

Applicant: Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

Inventor： Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

IPC: H01L21/44

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.

Abstract translation: 制造在电介质中包括通孔阵列的独立的隔离膜的方法用作在优异的电子支撑结构的结构中作为前体，包括在牺牲载体上的电介质环绕中制造导电通孔的膜的步骤， 膜从牺牲载体形成独立的层压阵列。 可以通过使叠层阵列变薄平坦化，然后终止来形成基于这种自立式膜的电子基板。

公开(公告)号：US07669320B2

公开(公告)日：2010-03-02

申请号：US11737269

申请日：2007-04-19

Applicant: Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

Inventor： Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

IPC: H05K3/10

CPC classification number: H01L21/4857 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/183 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract translation: 一种用于制造用于支撑与第二IC芯片串联连接的第一IC芯片的IC支架的方法; 所述IC支架包括一组交替的铜特征层和绝缘环绕的通孔，所述第一IC管芯可粘合到所述IC支架上，并且所述第二IC管芯可在所述IC支架内部的空腔内接合，其中所述空腔由 蚀刻铜基，并选择性地蚀刻掉铜层。

公开(公告)号：US06262376B1

公开(公告)日：2001-07-17

申请号：US09372601

申请日：1999-08-12

Applicant: Dror Hurwitz ,  Boris Yofis ,  Dror Katz ,  Eva Igner

Inventor： Dror Hurwitz ,  Boris Yofis ,  Dror Katz ,  Eva Igner

IPC: H05K103

CPC classification number: H05K3/4647 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: A chip carrier substrate including a lower layer and at least one upper layer of copper conductors on a base, a plurality of aluminum studs formed by anodization to be of substantially identical height which interconnect the layers of conductors, a layer of barrier metal electrically connecting the aluminum studs and the copper conductors to prevent direct contact therebetween, the aluminum studs and at least the upper layer of copper conductor being surrounded by a polymeric dielectric material, and a layer of adhesion/barrier metal beneath the upper copper conductor layer, between the upper copper conductor layer and the dielectric material.

Abstract translation: 一种芯片载体基板，包括下层和至少一层铜导体的基底上的多个铝螺柱，通过阳极氧化形成的具有基本上相同的高度的多个铝螺柱，其互连导体层，一层阻挡金属电连接 铝螺柱和铜导体，以防止它们之间的直接接触，铝螺柱和至少铜导体的上层被聚合物电介质材料包围，并且在上部铜导体层下面的上部铜导体层之间的粘附/阻挡金属层 铜导体层和电介质材料。