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    Field plate structures with patterned surface passivation layers and methods for manufacturing thereof
    3.
    发明授权
    Field plate structures with patterned surface passivation layers and methods for manufacturing thereof 有权

    公开(公告)号：US11121245B2

    公开(公告)日：2021-09-14

    申请号：US16793590

    申请日：2020-02-18

    Applicant: Efficient Power Conversion Corporation

    Inventor： Jianjun Cao ,  Jie Hu ,  Yoganand Saripalli ,  Muskan Sharma

    IPC: H01L29/778 ,  H01L29/78 ,  H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

    Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

    GATE WITH SELF-ALIGNED LEDGED FOR ENHANCEMENT MODE GaN TRANSISTORS
    7.
    发明申请
    GATE WITH SELF-ALIGNED LEDGED FOR ENHANCEMENT MODE GaN TRANSISTORS 有权
    具有自对准LED的增强型GaN晶体管的门

    公开(公告)号：US20160035847A1

    公开(公告)日：2016-02-04

    申请号：US14447069

    申请日：2014-07-30

    Applicant: Efficient Power Conversion Corporation

    Inventor： Jianjun Cao ,  Alexander Lidow ,  Alana Nakata

    IPC: H01L29/423 ,  H01L21/285 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

    CPC classification number: H01L29/42316 ,  H01L21/283 ,  H01L21/28587 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

    Abstract translation: 具有栅极接触和2DEG区域之间的栅极漏电流减小的增强型GaN晶体管及其制造方法。 包括GaN层的增强型GaN晶体管，在GaN层上设置有形成在GaN层和阻挡层之间的界面处的2DEG区域的势垒层，以及设置在阻挡层上的源极接触漏极触点。 该GaN晶体管还包括形成在阻挡层之上并且在源极和漏极接触之间以及设置在p型栅极材料上的栅极金属的p型栅极材料，其中p型栅极材料包括一对自身 对齐的突起分别延伸到源极接触和漏极接触。

    ISOLATION STRUCTURE IN GALLIUM NITRIDE DEVICES AND INTEGRATED CIRCUITS
    9.
    发明申请
    ISOLATION STRUCTURE IN GALLIUM NITRIDE DEVICES AND INTEGRATED CIRCUITS 有权
    氮化镓装置和集成电路中的隔离结构

    公开(公告)号：US20150008442A1

    公开(公告)日：2015-01-08

    申请号：US14322659

    申请日：2014-07-02

    Applicant: Efficient Power Conversion Corporation

    Inventor： Chunhua Zhou ,  Jianjun Cao ,  Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Robert Strittmatter ,  Guang Yuan Zhao ,  Seshadri Kolluri ,  Yanping Ma ,  Fang Chang ,  Ming-Kun Chiang ,  Jiali Cao

    IPC: H01L29/20 ,  H01L29/267 ,  H01L29/778

    CPC classification number: H01L29/2003 ,  H01L21/76 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

    Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.

    Abstract translation: 一种集成半导体器件，包括衬底层，形成在衬底层上的缓冲层，形成在缓冲层上的氮化镓层以及形成在氮化镓层上的阻挡层。 在阻挡层上形成多个晶体管器件的欧姆接触。 具体地说，用于第一晶体管器件的多个第一欧姆触点形成在阻挡层表面的第一部分上，并且用于第二晶体管器件的多个第二欧姆触点形成在第二晶体管器件的表面的第二部分上 阻挡层。 此外，形成在第一和第二晶体管器件之间的势垒表面的第三部分上的一个或多个栅极结构。 优选地，一个或多个栅极结构和晶体管器件的栅极结构和源极触点之间的空间共同形成将第一晶体管器件与第二晶体管器件电隔离的隔离区域。

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