公开(公告)号：US08918991B2

公开(公告)日：2014-12-30

申请号：US13289995

申请日：2011-11-04

Applicant: Eric R. Ao

Inventor： Eric R. Ao

IPC: H01K3/10 ,  H05K3/30 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K2201/09645 ,  Y10T29/49139 ,  Y10T29/49165

Abstract: The present invention relates to circuit boards and, more specifically, a process for providing electrical connections with reduced via capacitance on circuit boards. In one embodiment, the present invention provides a method for providing an electrical connection between traces disposed on different layers of a circuit board, the method comprising forming in the board a via hole that extends between the different layers and interconnects a pair of electrically conductive traces disposed on the different layers. An inner sidewall of the via hole includes electrically conductive material thereon. The method further comprises removing a first portion of the conductive material from the inner sidewall by removing a first portion of the inner sidewall. A remaining portion of the conductive material on a remaining portion of the inner sidewall interconnects the pair of traces and has a corresponding width that is substantially similar to a width of each trace.

Abstract translation: 本发明涉及电路板，更具体地说，涉及一种用于在电路板上提供减少的通孔电容的电连接的方法。 在一个实施例中，本发明提供了一种用于在布置在电路板的不同层上的迹线之间提供电连接的方法，所述方法包括在所述板中形成在不同层之间延伸的通孔，并且互连一对导电迹线 放置在不同的层上。 通孔的内侧壁包括导电材料。 该方法还包括通过去除内侧壁的第一部分从内侧壁去除导电材料的第一部分。 在内侧壁的剩余部分上的导电材料的剩余部分将一对迹线互连，并具有基本上类似于每个迹线的宽度的对应宽度。

公开(公告)号：US20130112470A1

公开(公告)日：2013-05-09

申请号：US13289987

申请日：2011-11-04

Applicant: Eric R. Ao

Inventor： Eric R. Ao

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/115 ,  H05K2203/0242

Abstract: The present invention relates to circuit boards and, more specifically, circuit boards with vias (i.e. via holes) exhibiting reduced via capacitance. In one embodiment, the present invention provides a circuit board comprising a first electrically conductive trace, a second electrically conductive trace, a via hole including electrically conductive material thereon, and a coupling element that electrically connects the first trace to the second trace. The coupling element comprises a segment of the via hole that bridges the first trace and the second trace, wherein the via hole segment is a remainder of the via hole after removal of a portion of the via hole.

Abstract translation: 本发明涉及电路板，更具体地，涉及具有减小的通孔电容的通孔（即通孔）的电路板。 在一个实施例中，本发明提供一种电路板，其包括第一导电迹线，第二导电迹线，在其上包括导电材料的通孔以及将第一迹线电连接到第二迹线的耦合元件。 耦合元件包括桥接第一迹线和第二迹线的通孔的一部分，其中通孔段是去除通孔的一部分后的通孔的剩余部分。

公开(公告)号：US09035197B2

公开(公告)日：2015-05-19

申请号：US13289987

申请日：2011-11-04

Applicant: Eric R. Ao

Inventor： Eric R. Ao

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/115 ,  H05K2203/0242

Abstract: The present invention relates to circuit boards and, more specifically, circuit boards with vias (i.e. via holes) exhibiting reduced via capacitance. In one embodiment, the present invention provides a circuit board comprising a first electrically conductive trace, a second electrically conductive trace, a via hole including electrically conductive material thereon, and a coupling element that electrically connects the first trace to the second trace. The coupling element comprises a segment of the via hole that bridges the first trace and the second trace, wherein the via hole segment is a remainder of the via hole after removal of a portion of the via hole.

Abstract translation: 本发明涉及电路板，更具体地，涉及具有减小的通孔电容的通孔（即通孔）的电路板。 在一个实施例中，本发明提供一种电路板，其包括第一导电迹线，第二导电迹线，在其上包括导电材料的通孔以及将第一迹线电连接到第二迹线的耦合元件。 耦合元件包括桥接第一迹线和第二迹线的通孔的一部分，其中通孔段是去除通孔的一部分后的通孔的剩余部分。

公开(公告)号：US20130111745A1

公开(公告)日：2013-05-09

申请号：US13289995

申请日：2011-11-04

Applicant: Eric R. Ao

Inventor： Eric R. Ao

IPC: H05K3/30

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K2201/09645 ,  Y10T29/49139 ,  Y10T29/49165

Abstract: The present invention relates to circuit boards and, more specifically, a process for providing electrical connections with reduced via capacitance on circuit boards. In one embodiment, the present invention provides a method for providing an electrical connection between traces disposed on different layers of a circuit board, the method comprising forming in the circuit board a via hole that interconnects a first electrically conductive trace and a second electrically conductive trace. The via hole includes electrically conductive material thereon. The method further comprises removing a portion of the electrically conductive material from the via hole.

Abstract translation: 本发明涉及电路板，更具体地说，涉及一种用于在电路板上提供减少的通孔电容的电连接的方法。 在一个实施例中，本发明提供了一种用于在布置在电路板的不同层上的迹线之间提供电连接的方法，所述方法包括在电路板中形成将第一导电迹线和第二导电迹线互连的通孔 。 通孔包括导电材料。 该方法还包括从通孔去除一部分导电材料。