公开(公告)号：US20200052704A1

公开(公告)日：2020-02-13

申请号：US16538569

申请日：2019-08-12

Applicant: Eta Compute, Inc.

Inventor： Gopal Raghavan

IPC: H03L1/02 ,  H03H9/19 ,  G06F1/14 ,  G06F1/08 ,  G06N3/08

Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

公开(公告)号：US20160328011A1

公开(公告)日：2016-11-10

申请号：US15210772

申请日：2016-07-14

Applicant: Eta Compute, Inc.

Inventor： Gopal Raghavan

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/172

Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.

Abstract translation: 公开了异步计算设备和操作异步计算设备的方法。 异步计算设备包括从工作电压和电压调节器电路操作的异步处理器。 异步处理器包括能够执行存储的指令的异步逻辑电路的集合。 电压调节器电路从异步处理器接收电压请求，并将工作电压输出到由电压请求定义的异步处理器。

公开(公告)号：US10732700B2

公开(公告)日：2020-08-04

申请号：US16233946

申请日：2018-12-27

Applicant: Eta Compute, Inc.

Inventor： Paul Murtagh ,  Gopal Raghavan

IPC: G06F1/324 ,  G06F1/28 ,  G06F1/12 ,  G06F1/3296 ,  G06F1/3234

Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.

公开(公告)号：US20190196564A1

公开(公告)日：2019-06-27

申请号：US16233946

申请日：2018-12-27

Applicant: Eta Compute, Inc.

Inventor： Paul Murtagh ,  Gopal Raghavan

IPC: G06F1/324 ,  G06F1/12 ,  G06F1/28

Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.

公开(公告)号：US10248187B2

公开(公告)日：2019-04-02

申请号：US15210772

申请日：2016-07-14

Applicant: Eta Compute, Inc.

Inventor： Gopal Raghavan

IPC: G06F1/3296 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/48

Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.

公开(公告)号：US20190325862A1

公开(公告)日：2019-10-24

申请号：US16392434

申请日：2019-04-23

Applicant: Eta Compute, Inc.

Inventor： Hari Shankar ,  Narayan Srinivasa ,  Gopal Raghavan ,  Chao Xu

IPC: G10L15/16 ,  G10L15/04 ,  G10L15/08 ,  G10L15/06

Abstract: Continuous automatic speech segmentation and recognition systems and methods are described that include a detector coupled to a neural network. The neural network performs speech recognition processing on feature vectors sequentially extracted from an audio data stream to attempt to recognize a word from a set of words of a predetermined vocabulary. The neural network has word neural paths to each output a respective word output signal to the detector for each of the set of words. The neural network also has a trigger neural path to output a trigger signal to the detector to control when the detector reviews the word output signals to recognize the word.

公开(公告)号：US20190190520A1

公开(公告)日：2019-06-20

申请号：US16270323

申请日：2019-02-07

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/017 ,  H03K19/177

CPC classification number: H03K19/003 ,  H03K19/01707 ,  H03K19/177

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

公开(公告)号：US10951212B2

公开(公告)日：2021-03-16

申请号：US16270323

申请日：2019-02-07

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/017

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

公开(公告)号：US10666268B2

公开(公告)日：2020-05-26

申请号：US16538569

申请日：2019-08-12

Applicant: Eta Compute, Inc.

Inventor： Gopal Raghavan

IPC: H03B5/32 ,  G06F1/14 ,  G06N3/08 ,  H03L1/02 ,  H03H9/19 ,  G06F1/08

Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

公开(公告)号：US10205453B2

公开(公告)日：2019-02-12

申请号：US15948733

申请日：2018-04-09

Applicant: Eta Compute, Inc.

Inventor： Chao Xu ,  Gopal Raghavan ,  Ben Wiley Melton ,  Vidura Manu Wijayasekara ,  Bryan Garnett Cope ,  David Cureton Baker ,  John Whitaker Havlicek

IPC: H03K19/003 ,  H03K19/177

Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.