公开(公告)号：US12159940B2

公开(公告)日：2024-12-03

申请号：US17575838

申请日：2022-01-14

Applicant: FLOSFIA INC.

Inventor： Mitsuru Okigawa ,  Yasushi Higuchi ,  Yusuke Matsubara ,  Osamu Imafuji ,  Takashi Shinohe

IPC: H01L29/872 ,  H01L21/02 ,  H01L29/04 ,  H01L29/24 ,  H01L29/47 ,  H01L29/78 ,  H01L29/786

Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.

公开(公告)号：US12107137B2

公开(公告)日：2024-10-01

申请号：US17834089

申请日：2022-06-07

Applicant: FLOSFIA INC.

Inventor： Mitsuru Okigawa ,  Fujio Okui ,  Yasushi Higuchi ,  Koji Amazutsumi ,  Hidetaka Shibata ,  Yuji Kato ,  Atsushi Terai

IPC: H01L29/06 ,  H01L29/47 ,  H01L29/872

CPC classification number: H01L29/475 ,  H01L29/0649 ,  H01L29/872

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n−-type semiconductor layer that is placed on the n+-type semiconductor layer, the n−-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n−-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 μm from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n−-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

公开(公告)号：US12289917B2

公开(公告)日：2025-04-29

申请号：US17834129

申请日：2022-06-07

Applicant: FLOSFIA INC.

Inventor： Mitsuru Okigawa ,  Fujio Okui ,  Yasushi Higuchi ,  Koji Amazutsumi ,  Hidetaka Shibata ,  Yuji Kato ,  Atsushi Terai

IPC: H10D8/60 ,  H10D62/80

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n−-type semiconductor layer that is placed on the n+-type semiconductor layer, the n−-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n−-type semiconductor layer, a depth d (μm) of the part embedded in the n−-type semiconductor layer satisfying d≥1.4; and a Schottky electrode that forms a Schottky junction with the n−-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

公开(公告)号：US20250133794A1

公开(公告)日：2025-04-24

申请号：US19005092

申请日：2024-12-30

Applicant: FLOSFIA INC

Inventor： Yusuke MATSUBARA ,  Mitsuru Okigawa ,  Hiroyuki Ando ,  Takashi Shinohe

IPC: H10D62/60 ,  H01L21/425 ,  H10D8/60 ,  H10D62/10 ,  H10D62/40 ,  H10D62/80

Abstract: Provided a semiconductor device including: a semiconductor layer; and an electrode disposed on the semiconductor layer directly or via another layer, the semiconductor layer including a first region containing, as a major component, a crystalline oxide semiconductor containing gallium, and a second region containing, as a major component, an oxide containing gallium, the second region and the first region each containing an impurity element, a maximum value of a concentration of the impurity element in the second region being located at a depth of 1.0 μm or more from an upper surface of the semiconductor layer and being greater than a maximum value of a concentration of the impurity element in the first region.

公开(公告)号：US12100769B2

公开(公告)日：2024-09-24

申请号：US17613346

申请日：2020-05-22

Applicant: FLOSFIA INC.

Inventor： Mitsuru Okigawa

IPC: H01L29/47 ,  H01L29/786 ,  H01L29/872

CPC classification number: H01L29/7869 ,  H01L29/47 ,  H01L29/872

Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer including an oxide semiconductor having a corundum structure as a main component, and a Schottky electrode including a first electrode layer and a second electrode layer having a higher conductivity than the first electrode layer, wherein an outer edge portion of the second electrode layer is electrically connected to the semiconductor layer at an electrical connection region through the first electrode layer, and an outer edge portion of the first electrode layer is located outside an outer edge portion of the electrical connection region.

公开(公告)号：US11855135B2

公开(公告)日：2023-12-26

申请号：US17508259

申请日：2021-10-22

Applicant: FLOSFIA INC.

Inventor： Mitsuru Okigawa ,  Hideaki Yanagida ,  Takashi Shinohe

IPC: H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66 ,  H01L29/872 ,  H02P27/06

CPC classification number: H01L29/0623 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7802 ,  H01L29/872 ,  H02P27/06

Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.