公开(公告)号：US10103060B2

公开(公告)日：2018-10-16

申请号：US14742895

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： David G. Brochu, Jr. ,  Roger A. Dufresne ,  Baozhen Li ,  Barry P. Linder ,  James H. Stathis ,  Ernest Y. Wu

IPC: H01L21/768 ,  H01L21/66 ,  G01R31/44 ,  G01R27/26 ,  G01R31/28

Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.

公开(公告)号：US20170221831A1

公开(公告)日：2017-08-03

申请号：US15014759

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US20170212165A1

公开(公告)日：2017-07-27

申请号：US15005819

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2858 ,  H01L22/14 ,  H01L22/20

Abstract: Disclosed herein are methods for making integrated circuit (IC) chip reliability estimations based on resistance measurements and for using such estimations to disposition manufactured chips. In the methods, a resistance-to-electromigration fail rate correlation can be empirically determined for an integrated circuit chip design. Additionally, for each chip manufactured according to the design, at least one resistance monitor can be used to acquire a resistance value for that manufactured chip. Then, given the resistance value and the resistance-to-electromigration fail rate correlation, the expected reliability of the manufactured chip can be estimated and the manufactured chip can be dispositioned in a variety of different ways.

公开(公告)号：US20160372389A1

公开(公告)日：2016-12-22

申请号：US14742895

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： David G. Brochu, JR. ,  Roger A. Dufresne ,  Baozhen Li ,  Barry P. Linder ,  James H. Stathis ,  Ernest Y. Wu

IPC: H01L21/66 ,  H01L21/768 ,  H01L29/66 ,  G01R31/28 ,  H01L21/28

CPC classification number: H01L21/76885 ,  G01R27/2617 ,  G01R31/2856 ,  G01R31/44 ,  H01L22/34

Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.

Abstract translation: 用于测试电介质材料可靠性的方法和测试结构。 测试结构可以包括第一行触点和由导体组成的线。 该线在与第一排触点最小距离的方向上横向隔开。 测试结构还包括第二排触点，其在与第一触点排的方向上横向间隔开等于最小间距的两倍的距离。 该线横向地位于第一排触点和第二排触点之间。

公开(公告)号：US10090240B2

公开(公告)日：2018-10-02

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US10062647B2

公开(公告)日：2018-08-28

申请号：US15646325

申请日：2017-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/538 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US20170352619A1

公开(公告)日：2017-12-07

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L28/60

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US09761526B2

公开(公告)日：2017-09-12

申请号：US15014759

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Baozhen Li

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257

Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.

公开(公告)号：US09639645B2

公开(公告)日：2017-05-02

申请号：US14742801

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5081

Abstract: Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

公开(公告)号：US09625325B2

公开(公告)日：2017-04-18

申请号：US14624907

申请日：2015-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G01R31/26 ,  G01K7/16 ,  G01L21/30 ,  G01R31/00 ,  G01N27/64 ,  G01N27/62 ,  G01N17/00 ,  G01N27/82 ,  G01R33/12 ,  G01N27/74 ,  H01J41/02 ,  H01J41/00

CPC classification number: G01K7/16 ,  G01L21/30 ,  G01N17/00 ,  G01N27/62 ,  G01N27/64 ,  G01R31/00 ,  H01J41/00 ,  H01J41/02 ,  H01L23/34

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.