公开(公告)号：US09484402B2

公开(公告)日：2016-11-01

申请号：US14662743

申请日：2015-03-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-chen Yeh

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/517 ,  H01L29/7846

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

公开(公告)号：US09337289B2

公开(公告)日：2016-05-10

申请号：US14571628

申请日：2014-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

公开(公告)号：US09570466B2

公开(公告)日：2017-02-14

申请号：US14159027

申请日：2014-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Cai ,  Dechao Guo ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/84 ,  H01L29/78 ,  H01L27/13

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/13

Abstract: Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.

Abstract translation: 提供了在极薄的绝缘体上硅（ETSOI）晶圆上制造无源器件的技术。 在一方面，提供了一种用于在ETSOI晶片中制造一个或多个无源器件的方法。 该方法包括以下步骤。 提供具有衬底的ETSOI晶片和通过掩埋氧化物（BOX）与衬底分离的ETSOI层。 ETSOI层涂有保护层。 形成延伸穿过保护层，ETSOI层和BOX的至少一个沟槽，并且其中衬底的一部分暴露在沟槽内。 在沟槽的侧壁上形成间隔物。 从衬底模板化的外延硅在沟槽中生长。 保护层从ETSOI层去除。 无源器件形成在外延硅中。

公开(公告)号：US09472640B2

公开(公告)日：2016-10-18

申请号：US14698206

申请日：2015-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/16 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/04 ,  H01L21/306 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L29/66045 ,  H01L21/02527 ,  H01L21/043 ,  H01L21/044 ,  H01L21/30604 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/0545

Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer.

Abstract translation: 具有自对准源极/漏极区域的晶体管及其制造方法。 所述方法包括形成嵌入衬底中的凹部中的栅极结构; 去除栅极结构周围的衬底材料以产生自对准的源极和漏极凹槽; 在栅极结构和源极和漏极凹槽上形成沟道层; 以及在源极和漏极凹槽中形成源极和漏极接触。 源极和漏极触点在沟道层上方延伸。