公开(公告)号：US09972697B2

公开(公告)日：2018-05-15

申请号：US15267887

申请日：2016-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09466692B2

公开(公告)日：2016-10-11

申请号：US14699746

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract translation: 一种制造用于半导体器件的替代栅极堆叠的方法包括在去除伪栅极之后的以下步骤：在由虚拟栅极空出的区域上生长高k电介质层; 在高k电介质层上沉积薄金属层; 在所述薄金属层上沉积牺牲层; 执行第一快速热退火; 去除牺牲层; 以及沉积用于间隙填充的低电阻率金属的金属层。

公开(公告)号：US20150243761A1

公开(公告)日：2015-08-27

申请号：US14699746

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US10361281B2

公开(公告)日：2019-07-23

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L29/423 ,  H01L21/3205

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US10083967B2

公开(公告)日：2018-09-25

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L21/764

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US20180197972A1

公开(公告)日：2018-07-12

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/28 ,  H01L29/423 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09960252B2

公开(公告)日：2018-05-01

申请号：US15258597

申请日：2016-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09599656B2

公开(公告)日：2017-03-21

申请号：US14553863

申请日：2014-11-25

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon ,  Eduard A. Cartier

IPC: G01R31/00 ,  G01R31/14 ,  G01R31/28

CPC classification number: G01R31/14 ,  G01R31/2879

Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

公开(公告)号：US20150243762A1

公开(公告)日：2015-08-27

申请号：US14699843

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20170358581A1

公开(公告)日：2017-12-14

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.