公开(公告)号：US11101010B2

公开(公告)日：2021-08-24

申请号：US16568394

申请日：2019-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. Hunt-Schroeder ,  Sebastian T. Ventrone ,  James A. Svarczkopf ,  Igor Arsovski

IPC: G11C17/18 ,  G11C7/06 ,  G11C7/08 ,  G11C11/409

Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.