公开(公告)号：US10741556B2

公开(公告)日：2020-08-11

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US10396078B2

公开(公告)日：2019-08-27

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US10388654B2

公开(公告)日：2019-08-20

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

公开(公告)号：US10204984B1

公开(公告)日：2019-02-12

申请号：US15667376

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Matthew W. Stoker ,  Judson R. Holt ,  Timothy J. McArdle ,  Annie Lévesque

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/108 ,  H01L21/02 ,  H01L29/423

Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.

公开(公告)号：US09923082B2

公开(公告)日：2018-03-20

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US20170117387A1

公开(公告)日：2017-04-27

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US20170033181A1

公开(公告)日：2017-02-02

申请号：US14810574

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Bharat V. Krishnan ,  Jody A. Fronheiser

IPC: H01L29/10 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/1054 ,  H01L21/02107 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.

Abstract translation: 本文中公开的一种说明性方法包括在衬底翅片腔中单独形成不同半导体材料的交替层，以在凹陷衬底鳍上方形成多层鳍，其中形成不同半导体材料的各层 到最终厚度小于所形成的不同半导体材料的层的临界厚度，使绝缘材料层凹陷，以便将多层鳍片的至少一部分暴露在层的凹陷的上表面上方 绝缘材料并围绕暴露的多层鳍片的至少一部分形成栅极结构。

公开(公告)号：US08779525B2

公开(公告)日：2014-07-15

申请号：US13772401

申请日：2013-02-21

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

公开(公告)号：US20130161759A1

公开(公告)日：2013-06-27

申请号：US13772401

申请日：2013-02-21

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

公开(公告)号：US10756184B2

公开(公告)日：2020-08-25

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Judson R. Holt ,  Steffen A. Sichler ,  Ömür I. Aydin ,  Wei Hong ,  Yi Qi ,  Hui Zang ,  Liu Jiang

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.