公开(公告)号：US10712498B2

公开(公告)日：2020-07-14

申请号：US16216321

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G02B27/01 ,  A61B3/113 ,  G02B6/34 ,  G02B6/42 ,  G02F1/29 ,  G02F1/313 ,  G06K9/00 ,  G06K9/62 ,  G02B27/00 ,  G02F1/31 ,  G02B6/122 ,  G02B6/136 ,  G02B6/125 ,  G02B6/132 ,  G02B6/12 ,  G02B1/04

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

公开(公告)号：US09269642B2

公开(公告)日：2016-02-23

申请号：US13915947

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael T. Coster ,  Mark A. DiRocco ,  Jeffrey P. Gambino ,  Kirk D. Peterson

IPC: H01L21/66 ,  H01L33/62 ,  H01L23/48

CPC classification number: H01L22/14 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

Abstract translation: 本发明的方面涉及测试晶片的集成电路和用于集成电路的测试结构的方法。 所述方法包括在集成电路的第一导体材料上沉积牺牲材料，并使测试探针与沉积的牺牲材料接触。 这些方法还可以包括使用与牺牲材料接触的测试探针来测试集成电路。 最后，该方法可以包括在集成电路的测试之后去除集成电路的第一导体材料上的牺牲材料。

公开(公告)号：US20180182778A1

公开(公告)日：2018-06-28

申请号：US15901997

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Terence B. Hook ,  Kirk D. Peterson

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/66 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L22/20 ,  H01L27/11 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4908 ,  H01L29/66568 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78696

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

公开(公告)号：US09575115B2

公开(公告)日：2017-02-21

申请号：US13649699

申请日：2012-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathaniel R. Chadwick ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Kirk D. Peterson ,  Andrew A. Turner

IPC: G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2872 ,  G01R31/2831 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

Abstract translation: 一种系统和方法对集成电路器件进行排序。 根据使用制造设备的集成电路设计，在晶片上制造集成电路器件。 该设计生产的集成电路器件根据制造工艺变化相同设计和执行不同。 集成电路设备在使用时可用于一系列环境条件。 在集成电路器件上进行测试。 每个设备单独预测环境最大值。 环境最大值包括每个设备在给定故障率以上执行时不得超过的环境条件。 基于为每个设备预测的环境最大值，为每个集成电路设备分配多个等级中的至少一个。 基于分配给每个设备的等级，将集成电路设备提供给具有不同环境条件的不同服务形式。

公开(公告)号：US10090330B2

公开(公告)日：2018-10-02

申请号：US15901997

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Terence B. Hook ,  Kirk D. Peterson

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/66 ,  H01L21/84 ,  H01L27/11 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

公开(公告)号：US09299769B2

公开(公告)日：2016-03-29

申请号：US14151550

申请日：2014-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/06 ,  H01L21/76254

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract translation: 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。