公开(公告)号：US10700013B2

公开(公告)日：2020-06-30

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US20160240479A1

公开(公告)日：2016-08-18

申请号：US14624907

申请日：2015-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: H01L23/525 ,  G01K7/16 ,  H01L23/532 ,  G01N25/00

CPC classification number: G01K7/16 ,  G01L21/30 ,  G01N17/00 ,  G01N27/62 ,  G01N27/64 ,  G01R31/00 ,  H01J41/00 ,  H01J41/02 ,  H01L23/34

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.

Abstract translation: 本公开的方面包括用于识别集成电路（IC）的工作温度的计算机实现的方法，所述方法包括使用计算设备：将测试电压施加到嵌入在所述IC内的测试电路，所述测试电路包括 在其中的相移存储器（PSM）元件，其中所述PSM元件在结晶温度下从具有第一电阻的非晶相结晶成具有第二电阻的晶相，所述第二电阻小于所述第一电阻; 以及响应于所述测试电压在所述测试电压处于目标工作范围之外的电阻而将所述IC识别为高于所述结晶温度的IC。

公开(公告)号：US09639645B2

公开(公告)日：2017-05-02

申请号：US14742801

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5081

Abstract: Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

公开(公告)号：US09625325B2

公开(公告)日：2017-04-18

申请号：US14624907

申请日：2015-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G01R31/26 ,  G01K7/16 ,  G01L21/30 ,  G01R31/00 ,  G01N27/64 ,  G01N27/62 ,  G01N17/00 ,  G01N27/82 ,  G01R33/12 ,  G01N27/74 ,  H01J41/02 ,  H01J41/00

CPC classification number: G01K7/16 ,  G01L21/30 ,  G01N17/00 ,  G01N27/62 ,  G01N27/64 ,  G01R31/00 ,  H01J41/00 ,  H01J41/02 ,  H01L23/34

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.

公开(公告)号：US09618566B2

公开(公告)日：2017-04-11

申请号：US14620273

申请日：2015-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G01R31/28 ,  G06F21/57 ,  H05K13/08

CPC classification number: G01R31/2851 ,  G01R31/2813 ,  G06F21/575 ,  H05K13/0486 ,  H05K13/08

Abstract: In the systems and methods, an identifier is generated for a printed circuit board (PCB), chips are connected to the PCB, and corresponding sets of programmable bits on the chips are programmed to match specific sections of the identifier. Due to the generation of the identifier and the programming of the corresponding sets of programmable bits on the chips to match specific sections of the identifier, the validity of the chips can be verified at any time during product life. For example, for each chip, its set of programmable bits can be read and, then, a determination can be made as to whether that set of programmable bits is indeed programmed to match a specific section of the identifier. Operation of the PCB can be allowed when all the chips are determined to be valid and prohibited when any of the chips are determined to be invalid (e.g., previously used).

公开(公告)号：US20190214348A1

公开(公告)日：2019-07-11

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US20170212165A1

公开(公告)日：2017-07-27

申请号：US15005819

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

IPC: G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2858 ,  H01L22/14 ,  H01L22/20

Abstract: Disclosed herein are methods for making integrated circuit (IC) chip reliability estimations based on resistance measurements and for using such estimations to disposition manufactured chips. In the methods, a resistance-to-electromigration fail rate correlation can be empirically determined for an integrated circuit chip design. Additionally, for each chip manufactured according to the design, at least one resistance monitor can be used to acquire a resistance value for that manufactured chip. Then, given the resistance value and the resistance-to-electromigration fail rate correlation, the expected reliability of the manufactured chip can be estimated and the manufactured chip can be dispositioned in a variety of different ways.