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    Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
    2.
    发明授权
    Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices 有权
    在半导体器件上形成自对准接触结构的方法和所得到的器件

    公开(公告)号：US09502286B2

    公开(公告)日：2016-11-22

    申请号：US14674460

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

    IPC: H01L21/44 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

    CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

    Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

    Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

    Methods of forming contacts on semiconductor devices and the resulting devices
    3.
    发明授权
    Methods of forming contacts on semiconductor devices and the resulting devices 有权
    在半导体器件上形成触点的方法和所得到的器件

    公开(公告)号：US09324656B1

    公开(公告)日：2016-04-26

    申请号：US14641551

    申请日：2015-03-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andre Labonte ,  Ruilong Xie

    IPC: H01L29/02 ,  H01L23/535 ,  H01L21/768

    CPC classification number: H01L29/785 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method of forming a transistor device comprised of a source/drain region and a gate structure includes forming a dielectric layer above the gate structure and the source/drain region. A first opening is formed in at least the dielectric layer to expose the gate structure. A first spacer is formed on sidewalls of the first opening. After forming the first spacer, a second opening is formed in at least the dielectric layer to expose a portion of the source/drain region. The first spacer at least partially defines a spacing between the first opening and the second opening. A conductive gate contact is formed in the first opening and a conductive source/drain contact is formed in the second opening.

    Abstract translation: 形成由源极/漏极区域和栅极结构构成的晶体管器件的一种方法包括在栅极结构和源极/漏极区域上方形成介电层。 至少在电介质层中形成第一开口以露出栅极结构。 第一间隔件形成在第一开口的侧壁上。 在形成第一间隔物之后，在至少介电层中形成第二开口以暴露源/漏区的一部分。 第一间隔件至少部分地限定第一开口和第二开口之间的间隔。 在第一开口中形成导电栅极接触，并且在第二开口中形成导电源极/漏极接触。

    Middle of the line (MOL) contacts with two-dimensional self-alignment
    5.
    发明授权
    Middle of the line (MOL) contacts with two-dimensional self-alignment 有权

    公开(公告)号：US10283408B2

    公开(公告)日：2019-05-07

    申请号：US15851774

    申请日：2017-12-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

    IPC: H01L29/78 ,  H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L29/49

    Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

    Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor
    6.
    发明授权
    Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor 有权

    公开(公告)号：US10211100B2

    公开(公告)日：2019-02-19

    申请号：US15469701

    申请日：2017-03-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

    IPC: H01L21/764 ,  H01L21/768

    Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

    Gate contact structure positioned above an active region of a transistor device
    8.
    发明授权
    Gate contact structure positioned above an active region of a transistor device 有权

    公开(公告)号：US10243053B1

    公开(公告)日：2019-03-26

    申请号：US15876316

    申请日：2018-01-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Andre Labonte ,  Chanro Park

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/28 ,  H01L23/528 ,  H01L29/78

    Abstract: One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.

    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    9.
    发明申请
    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    在半导体器件和结构器件上形成自对准接触结构的方法

    公开(公告)号：US20160163585A1

    公开(公告)日：2016-06-09

    申请号：US14674460

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

    IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

    CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

    Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

    Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

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