公开(公告)号：US20170104005A1

公开(公告)日：2017-04-13

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0696 ,  H01L29/4916 ,  H01L29/78648

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US20170243894A1

公开(公告)日：2017-08-24

申请号：US15049572

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ingolf Lorenz ,  Stefan Block ,  Ulrich Hensel ,  Jürgen Faul ,  Michael Zier ,  Haritez Narisetty

IPC: H01L27/12 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L27/1207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/66568 ,  H01L29/861

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

公开(公告)号：US10068918B2

公开(公告)日：2018-09-04

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US09773811B2

公开(公告)日：2017-09-26

申请号：US15049572

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ingolf Lorenz ,  Stefan Block ,  Ulrich Hensel ,  Jürgen Faul ,  Michael Zier ,  Haritez Narisetty

IPC: H01L27/12 ,  H01L23/62 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/66568 ,  H01L29/861

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.