公开(公告)号：US20180158833A1

公开(公告)日：2018-06-07

申请号：US15883975

申请日：2018-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L27/11531 ,  H01L27/11534 ,  H01L27/11529 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11524

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

公开(公告)号：US09922986B2

公开(公告)日：2018-03-20

申请号：US15155483

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L29/66 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11519 ,  H01L29/43

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

公开(公告)号：US20170330889A1

公开(公告)日：2017-11-16

申请号：US15155483

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11519 ,  H01L29/43

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

公开(公告)号：US10580863B2

公开(公告)日：2020-03-03

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L27/088 ,  H01L21/336 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L21/225 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US20180358259A1

公开(公告)日：2018-12-13

申请号：US15618491

申请日：2017-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo P. Mikalo ,  Martin Gerhardt

IPC: H01L21/76 ,  H01L49/02 ,  H01L23/367

CPC classification number: H01L21/76 ,  H01L23/367 ,  H01L28/20

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.

公开(公告)号：US09425194B2

公开(公告)日：2016-08-23

申请号：US14819646

申请日：2015-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。

公开(公告)号：US20190109192A1

公开(公告)日：2019-04-11

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US10256134B2

公开(公告)日：2019-04-09

申请号：US15618491

申请日：2017-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ricardo P. Mikalo ,  Martin Gerhardt

IPC: H01L21/20 ,  H01L21/76 ,  H01L49/02 ,  H01L23/367

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.

公开(公告)号：US09461145B2

公开(公告)日：2016-10-04

申请号：US14503810

申请日：2014-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Jan Hoentschel ,  Martin Gerhardt

IPC: H01L21/3213 ,  G03F1/36 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  G03F1/72 ,  H01L21/033

CPC classification number: H01L29/66545 ,  G03F1/72 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract translation: 通过OPC切割掩模校正将虚拟电极放大到STI顶部宽度尺寸，并且公开了所得到的器件。 实施例包括在硅衬底中形成STI区域，STI区域具有顶部宽度; 在STI区域上形成虚设电极，在硅衬底上形成栅电极，该虚拟电极的宽度大于或等于STI区域顶部宽度。

公开(公告)号：US20150340362A1

公开(公告)日：2015-11-26

申请号：US14819646

申请日：2015-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。