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    Nitride spacer for protecting a fin-shaped field effect transistor (finFET) device
    1.
    发明授权
    Nitride spacer for protecting a fin-shaped field effect transistor (finFET) device 有权
    用于保护鳍状场效应晶体管（finFET）器件的氮化物间隔物

    公开(公告)号：US09306036B2

    公开(公告)日：2016-04-05

    申请号：US13953833

    申请日：2013-07-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael Ganz

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/02362 ,  G06F17/505 ,  G06F2217/02 ,  H01L21/0217 ,  H01L27/0207 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

    Abstract: Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

    Abstract translation: 提供了使用氮化物间隔物来保护半导体器件（例如，鳍式场效应晶体管器件（FinFET））的方法。 具体地说，在FinFET器件的一个氧化物和一组鳍片之上形成一个氮化物间隔物，以减轻随后的处理过程中的损坏。 在阻挡层之前沉积氮化物间隔物，以在未被光致抗蚀剂覆盖的FinFET器件的开放区域中的一组栅极的顶部上保护氧化物。 每个栅极顶部的氧化物将保留在所有块层中，以在随后的源/漏外延层分层期间提供硬掩模保护。 此外，由光致抗蚀剂或该组栅极打开和未覆盖的翅片仍然被氮化物间隔物保护。 因此，防止由于暴露于抗蚀剂剥离处理的翅片的非晶化而引起的翅片侵蚀，从而提高了器件的产率。

    FinFET semiconductor structures and methods of fabricating same
    6.
    发明授权
    FinFET semiconductor structures and methods of fabricating same 有权

    公开(公告)号：US10096488B2

    公开(公告)日：2018-10-09

    申请号：US15608283

    申请日：2017-05-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Michael Ganz ,  Bingwu Liu ,  Johannes Marinus Van Meer ,  Sruthi Muralidharan

    IPC: H01L21/02 ,  H01L21/266 ,  H01L29/78 ,  H01L21/324 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/265 ,  H01L21/268 ,  H01L21/3105

    Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

    METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES
    8.
    发明申请
    METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES 有权
    在CMOS应用中形成晶体管的方法和结构化器件结构

    公开(公告)号：US20140367787A1

    公开(公告)日：2014-12-18

    申请号：US13918536

    申请日：2013-06-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

    IPC: H01L27/092 ,  H01L21/8234

    CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

    Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

    Abstract translation: 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

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