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    Technique for defining active regions of semiconductor devices with reduced lithography effort
    1.
    发明授权
    Technique for defining active regions of semiconductor devices with reduced lithography effort 有权

    公开(公告)号：US10199259B1

    公开(公告)日：2019-02-05

    申请号：US15670465

    申请日：2017-08-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Michael Zier

    IPC: H01L21/308 ,  H01L21/762 ,  G03F7/00 ,  G03F7/20 ,  G03F1/00

    Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

    TECHNIQUE FOR DEFINING ACTIVE REGIONS OF SEMICONDUCTOR DEVICES WITH REDUCED LITHOGRAPHY EFFORT
    3.
    发明申请
    TECHNIQUE FOR DEFINING ACTIVE REGIONS OF SEMICONDUCTOR DEVICES WITH REDUCED LITHOGRAPHY EFFORT 审中-公开

    公开(公告)号：US20190043752A1

    公开(公告)日：2019-02-07

    申请号：US15670465

    申请日：2017-08-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Michael Zier

    IPC: H01L21/762

    Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

    Contacting SOI subsrates
    5.
    发明授权
    Contacting SOI subsrates 有权

    公开(公告)号：US10068918B2

    公开(公告)日：2018-09-04

    申请号：US15375890

    申请日：2016-12-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

    IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06

    Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

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