公开(公告)号：US20180053829A1

公开(公告)日：2018-02-22

申请号：US15242689

申请日：2016-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sylvain Henri Baudot ,  Peter Javorka ,  Gerd Zschaetzsch

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/66628 ,  H01L29/786

Abstract: A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate structure, the raised source/drain regions being formed at opposing sides of the shaped gate structure relative to a length direction of the shaped gate structure, wherein the gate electrode has a tapering shape according to which a dimension of the gate electrode along the length direction varies from a maximum value at a lower portion of the gate electrode close to the gate dielectric layer towards a minimal value at a top portion of the gate electrode.

公开(公告)号：US20170338343A1

公开(公告)日：2017-11-23

申请号：US15161604

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sylvain Henri Baudot ,  Gunter Grasshoff ,  Juergen Faul ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/76 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7831 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided comprising a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and a transistor device, wherein the transistor device comprises a gate electrode formed by a part of the semiconductor bulk substrate, a gate insulation layer formed by a part of the buried oxide layer and a channel region formed in a part of the semiconductor layer.

公开(公告)号：US09536974B2

公开(公告)日：2017-01-03

申请号：US14689181

申请日：2015-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sylvain Henri Baudot

IPC: H01L21/32 ,  H01L29/49 ,  H01L29/40 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/324 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method of forming a semiconductor device is provided including forming a gate structure comprising a metal-containing layer over a semiconductor layer and doping the metal-containing layer by tilted ion implantation.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体层上形成包括含金属层的栅极结构，并通过倾斜离子注入掺杂含金属层。

公开(公告)号：US20160308017A1

公开(公告)日：2016-10-20

申请号：US14689181

申请日：2015-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sylvain Henri Baudot

IPC: H01L29/49 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L29/417 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/4966 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/324 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method of forming a semiconductor device is provided including forming a gate structure comprising a metal-containing layer over a semiconductor layer and doping the metal-containing layer by tilted ion implantation.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体层上形成包括含金属层的栅极结构，并通过倾斜离子注入掺杂含金属层。

公开(公告)号：US09876111B2

公开(公告)日：2018-01-23

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20170170317A1

公开(公告)日：2017-06-15

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.