公开(公告)号：US09054207B2

公开(公告)日：2015-06-09

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

公开(公告)号：US08786027B2

公开(公告)日：2014-07-22

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/76 ,  H01L29/34 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

公开(公告)号：US20130240988A1

公开(公告)日：2013-09-19

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

公开(公告)号：US09490189B2

公开(公告)日：2016-11-08

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38 ,  H01L35/32 ,  G06F1/20 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US20140238045A1

公开(公告)日：2014-08-28

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US20130299891A1

公开(公告)日：2013-11-14

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。