公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US20200027979A1

公开(公告)日：2020-01-23

申请号：US16038384

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

公开(公告)号：US10361289B1

公开(公告)日：2019-07-23

申请号：US15933032

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Shahab Siddiqui ,  Haiting Wang ,  Ting-Hsiang Hung ,  Yiheng Xu ,  Beth Baumert ,  Jinping Liu ,  Scott Beasor ,  Yue Zhong ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

公开(公告)号：US10784143B2

公开(公告)日：2020-09-22

申请号：US16263650

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang ,  Yue Zhong

IPC: H01L29/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/3213 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

公开(公告)号：US10153209B1

公开(公告)日：2018-12-11

申请号：US15888408

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L27/02 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US20200251377A1

公开(公告)日：2020-08-06

申请号：US16263650

申请日：2019-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang ,  Yue Zhong

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.

公开(公告)号：US10431499B2

公开(公告)日：2019-10-01

申请号：US16134650

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US20190244865A1

公开(公告)日：2019-08-08

申请号：US16134650

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66545

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.