公开(公告)号：US20230253017A1

公开(公告)日：2023-08-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming YIN ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US20230186980A1

公开(公告)日：2023-06-15

申请号：US17546408

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gregory A. Northrop ,  Vivek Raj ,  Amlan Bag ,  Shashank Nemawarkar

IPC: G11C11/419 ,  G06F30/327 ,  G06F30/3315

CPC classification number: G11C11/419 ,  G06F30/327 ,  G06F30/3315 ,  G11C11/412

Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.

公开(公告)号：US11635958B1

公开(公告)日：2023-04-25

申请号：US17567209

申请日：2022-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Gregory A. Northrop ,  Shashank Nemawarkar ,  Shivraj Gurpadappa Dharne

IPC: G06F9/30 ,  G06F7/544

Abstract: Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.

公开(公告)号：US12293086B2

公开(公告)日：2025-05-06

申请号：US18315696

申请日：2023-05-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shashank Nemawarkar ,  Bipul C. Paul

IPC: G06F3/06

Abstract: An apparatus and method for providing high throughput memory responses are provided. The apparatus includes a memory device including a plurality of memory arrays, a memory controller configured to control the memory device, the memory controller having a read queue, a write queue, and an address match circuit, and a data output circuit. The memory controller receives a read request, searches the write queue for a write address that matches a read address of the read request, and sends data associated with the write address from the write queue to the data output circuit without accessing the memory device when the write address matches the read address, the write address that matches the read address being a target address. The data output circuit outputs the data associated with the target address to an external device.

公开(公告)号：US12087384B2

公开(公告)日：2024-09-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.