公开(公告)号：US20240221810A1

公开(公告)日：2024-07-04

申请号：US18607725

申请日：2024-03-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

公开(公告)号：US20240194253A1

公开(公告)日：2024-06-13

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L29/40111

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：US11984160B2

公开(公告)日：2024-05-14

申请号：US17679207

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Periyapatna G. Venkatesh

IPC: G11C11/00 ,  G11C13/00 ,  H04L9/32

CPC classification number: G11C13/0059 ,  G11C13/004 ,  G11C13/0069 ,  H04L9/3278

Abstract: Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

公开(公告)号：US12136468B2

公开(公告)日：2024-11-05

申请号：US18045529

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10 ,  G11C7/12 ,  G11C13/00

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

公开(公告)号：US20240119977A1

公开(公告)日：2024-04-11

申请号：US18045520

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1096 ,  G11C7/067 ,  G11C7/1063 ,  G11C7/12

Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements connected between input nodes and a bitline. Each memory element includes a programmable resistor with an input connected to an input node and an output connected to the bitline. Each bank includes a feedback buffer connected to the bitline and an output node. Output nodes of banks in the same column are connected to the same column interconnect line. The initial bank in each row includes amplifiers connected between the input nodes and the memory elements, respectively. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.

公开(公告)号：US12176023B2

公开(公告)日：2024-12-24

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：US12159685B2

公开(公告)日：2024-12-03

申请号：US18045545

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：US20240119975A1

公开(公告)日：2024-04-11

申请号：US18045545

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1084 ,  G11C7/1096

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：US20230267998A1

公开(公告)日：2023-08-24

申请号：US17679207

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Periyapatna G. Venkatesh

IPC: G11C13/00 ,  H04L9/32

CPC classification number: G11C13/0059 ,  G11C13/004 ,  G11C13/0069 ,  H04L9/3278

Abstract: Circuits that include resistive memory elements and methods of using such circuits to generate a physical unclonable function. The circuit includes a first resistive memory element, a second resistive memory element, a first transistor having a source/drain region connected to the first resistive memory element, and a second transistor having a source/drain region connected to the second resistive memory element. The circuit further includes a first inverter having an input connected to a first node between the first transistor and the first resistive memory element, and a second inverter having an input connected to a second node between the second transistor and the second resistive memory element.

公开(公告)号：US12211585B2

公开(公告)日：2025-01-28

申请号：US18045520

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

Abstract: A structure for in-memory serial processing includes a memory bank array. Each bank includes memory elements connected between input nodes and a bitline. Each memory element includes a programmable resistor with an input connected to an input node and an output connected to the bitline. Each bank includes a feedback buffer connected to the bitline and an output node. Output nodes of banks in the same column are connected to the same column interconnect line. The initial bank in each row includes amplifiers connected between the input nodes and the memory elements, respectively. Outputs of these amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks. The amplifiers, feedback buffers, and voltage buffers minimize local IR drops and thereby processing errors.