公开(公告)号：US12050485B2

公开(公告)日：2024-07-30

申请号：US17726171

申请日：2022-04-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

IPC: G06F1/10 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F1/10 ,  G06F15/7839

Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

公开(公告)号：US20230341888A1

公开(公告)日：2023-10-26

申请号：US17726171

申请日：2022-04-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

IPC: G06F1/10 ,  G06F15/78

CPC classification number: G06F1/10 ,  G06F15/7839

Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

公开(公告)号：US20220215872A1

公开(公告)日：2022-07-07

申请号：US17143193

申请日：2021-01-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

公开(公告)号：US12183394B2

公开(公告)日：2024-12-31

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/419 ,  H03K3/356

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230326520A1

公开(公告)日：2023-10-12

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H03K3/356

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356078 ,  H03K3/356026

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US11621035B1

公开(公告)日：2023-04-04

申请号：US17447841

申请日：2021-09-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC: G11C8/10 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.

公开(公告)号：US11322200B1

公开(公告)日：2022-05-03

申请号：US17120325

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

公开(公告)号：US11900996B2

公开(公告)日：2024-02-13

申请号：US17504558

申请日：2021-10-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Bhuvan R. Nandagopal ,  Shivraj G. Dharne

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.

公开(公告)号：US11862240B2

公开(公告)日：2024-01-02

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C16/10 ,  G11C11/419 ,  H03K3/356 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356026 ,  H03K3/356078

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230186980A1

公开(公告)日：2023-06-15

申请号：US17546408

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gregory A. Northrop ,  Vivek Raj ,  Amlan Bag ,  Shashank Nemawarkar

IPC: G11C11/419 ,  G06F30/327 ,  G06F30/3315

CPC classification number: G11C11/419 ,  G06F30/327 ,  G06F30/3315 ,  G11C11/412

Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.