公开(公告)号：US11907408B2

公开(公告)日：2024-02-20

申请号：US17215746

申请日：2021-03-29

Applicant: Graphcore Limited

Inventor： Graham Cunningham ,  Daniel Wilkinson

IPC: G06F21/72 ,  G06F21/78 ,  H04L9/06 ,  H04L9/14 ,  H04L9/08 ,  G06F3/06 ,  H04L9/32

CPC classification number: G06F21/72 ,  G06F3/0623 ,  G06F3/0659 ,  G06F3/0683 ,  G06F21/78 ,  H04L9/0618 ,  H04L9/0631 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3242

Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to be handled by the encryption unit, since associated state information for each set of processors is independently maintained.

公开(公告)号：US11449117B2

公开(公告)日：2022-09-20

申请号：US16842859

申请日：2020-04-08

Applicant: Graphcore Limited

Inventor： Stephen Felix ,  Daniel Wilkinson

IPC: G06F1/30 ,  G06F1/08 ,  G06F1/3206

Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.

公开(公告)号：US11940940B2

公开(公告)日：2024-03-26

申请号：US17658944

申请日：2022-04-12

Applicant: Graphcore Limited

Inventor： Daniel Wilkinson ,  Stephen Felix ,  Simon Knowles ,  Graham Cunningham ,  David Lacey

IPC: G06F13/40 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F13/4022 ,  G06F9/30079 ,  G06F9/522 ,  G06F13/4027

Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.

公开(公告)号：US20220083695A1

公开(公告)日：2022-03-17

申请号：US17215746

申请日：2021-03-29

Applicant: Graphcore Limited

Inventor： Graham Cunningham ,  Daniel Wilkinson

IPC: G06F21/72 ,  H04L9/32 ,  H04L9/06 ,  G06F3/06

Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to he handled by the encryption unit, since associated state information for each set of processors is independently maintained.

公开(公告)号：US11822427B2

公开(公告)日：2023-11-21

申请号：US17823131

申请日：2022-08-30

Applicant: Graphcore Limited

Inventor： Stephen Felix ,  Daniel Wilkinson ,  Graham Bernard Cunningham

IPC: G06F11/10 ,  G06F11/07 ,  H03K19/21

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1004 ,  H03K19/21

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.

公开(公告)号：US11695709B2

公开(公告)日：2023-07-04

申请号：US17658955

申请日：2022-04-12

Applicant: Graphcore Limited

Inventor： Daniel Wilkinson ,  Graham Cunningham ,  Hachem Yassine

IPC: H04L12/28 ,  H04L49/9047 ,  H04L49/90 ,  H04L47/52 ,  H04L49/00 ,  H04L47/62

CPC classification number: H04L49/9047 ,  H04L47/52 ,  H04L47/6225 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/9026

Abstract: A hardware module comprises at least a first ingress buffer and a second ingress buffer, where the second ingress buffer holds data packets from a plurality of source components. To ensure fairness between one or more sources providing data to the first ingress buffer and the plurality of sources providing data to the second ingress buffer, processing circuitry examines source identifiers in packets held in the second ingress buffer and selects between the buffers so as to arbitrate between the sources. In some embodiments, the examination of the source identifiers provides statistics for a weighted round robin between the ingress buffers. In other embodiments, the source identifier of whichever packet is currently at the head of the second ingress buffer is used to perform a simple round robin between the sources.

公开(公告)号：US11461175B1

公开(公告)日：2022-10-04

申请号：US17447954

申请日：2021-09-17

Applicant: Graphcore Limited

Inventor： Stephen Felix ,  Daniel Wilkinson ,  Graham Bernard Cunningham

IPC: G06F11/00 ,  G06F11/10 ,  H03K19/21 ,  G06F11/07

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.