公开(公告)号：US11695709B2

公开(公告)日：2023-07-04

申请号：US17658955

申请日：2022-04-12

Applicant: Graphcore Limited

Inventor： Daniel Wilkinson ,  Graham Cunningham ,  Hachem Yassine

IPC: H04L12/28 ,  H04L49/9047 ,  H04L49/90 ,  H04L47/52 ,  H04L49/00 ,  H04L47/62

CPC classification number: H04L49/9047 ,  H04L47/52 ,  H04L47/6225 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/9026

Abstract: A hardware module comprises at least a first ingress buffer and a second ingress buffer, where the second ingress buffer holds data packets from a plurality of source components. To ensure fairness between one or more sources providing data to the first ingress buffer and the plurality of sources providing data to the second ingress buffer, processing circuitry examines source identifiers in packets held in the second ingress buffer and selects between the buffers so as to arbitrate between the sources. In some embodiments, the examination of the source identifiers provides statistics for a weighted round robin between the ingress buffers. In other embodiments, the source identifier of whichever packet is currently at the head of the second ingress buffer is used to perform a simple round robin between the sources.

公开(公告)号：US12047486B2

公开(公告)日：2024-07-23

申请号：US17359066

申请日：2021-06-25

Applicant: Graphcore Limited

Inventor： Graham Cunningham

IPC: H04L9/06

CPC classification number: H04L9/0618 ,  H04L9/0643

Abstract: The device implements a processing pipeline having distinct circuitry for performing encryption/decryption operations and authentication operations and having state stores associated with the respective operations. The state stores store state associated with a given encryption frame, enabling the respective operations to be performed when blocks of data reach that stage in the pipeline. Due to the complexity of operations in a block cipher encryption scheme, the pipeline is deep, which provide the possibility for processing multiple data packets at any one time. The provision of the state stores at the stages in the pipeline at which they are required prevents stalling when a new data packet is received.

公开(公告)号：US11907408B2

公开(公告)日：2024-02-20

申请号：US17215746

申请日：2021-03-29

Applicant: Graphcore Limited

Inventor： Graham Cunningham ,  Daniel Wilkinson

IPC: G06F21/72 ,  G06F21/78 ,  H04L9/06 ,  H04L9/14 ,  H04L9/08 ,  G06F3/06 ,  H04L9/32

CPC classification number: G06F21/72 ,  G06F3/0623 ,  G06F3/0659 ,  G06F3/0683 ,  G06F21/78 ,  H04L9/0618 ,  H04L9/0631 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3242

Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to be handled by the encryption unit, since associated state information for each set of processors is independently maintained.

公开(公告)号：US11940940B2

公开(公告)日：2024-03-26

申请号：US17658944

申请日：2022-04-12

Applicant: Graphcore Limited

Inventor： Daniel Wilkinson ,  Stephen Felix ,  Simon Knowles ,  Graham Cunningham ,  David Lacey

IPC: G06F13/40 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F13/4022 ,  G06F9/30079 ,  G06F9/522 ,  G06F13/4027

Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.

公开(公告)号：US20220083695A1

公开(公告)日：2022-03-17

申请号：US17215746

申请日：2021-03-29

Applicant: Graphcore Limited

Inventor： Graham Cunningham ,  Daniel Wilkinson

IPC: G06F21/72 ,  H04L9/32 ,  H04L9/06 ,  G06F3/06

Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to he handled by the encryption unit, since associated state information for each set of processors is independently maintained.