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1.发明授权公开(公告)号：US12119061B2
公开(公告)日：2024-10-15
申请号：US17841542
申请日：2022-06-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
CPC classification number: G11C15/046 , G06F3/0604 , G06F16/3341 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells. The method further includes applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause, randomly selecting one matched match line, determining a selected clause from one or more violated clause, and altering one or more literals within the interpretation using a break count for each variable of the selected clause.
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公开(公告)号：US20240315053A1
公开(公告)日：2024-09-19
申请号：US18184222
申请日：2023-03-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： JINSUNG YOUN , Xia Sheng , James Ignowski , Darrin Miller , Catherine Graves
CPC classification number: H10B80/00 , H01L24/16 , H01L24/17 , H01L23/481 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/1433 , H01L2924/1443
Abstract: Examples of the present technology provide heterogeneous (i.e., multi-chip) ASIC-memristor integrations that enable high voltage-dependent precision memristor programming while preserving optimal ASIC performance/capabilities. Examples achieve these advantages by “de-coupling” memristor hardware from ASIC chip. Accordingly, a heterogeneous ASIC-memristor integration of the present technology may comprise an ASIC chip packaged onto a functional “memristor-interposer” chip. The memristor interposer may serve both a functional and structural purpose. Namely, memristors of the memristor interposer can be leveraged in conjunction with the ASIC for processing/computation functions—while connections within the memristor interposer route signals between ASIC and computing system (e.g., between the ASIC and a printed circuit board).
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公开(公告)号：US11923009B2
公开(公告)日：2024-03-05
申请号：US17841532
申请日：2022-06-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
CPC classification number: G11C15/046 , H03K19/20
Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.
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公开(公告)号：US11783907B2
公开(公告)日：2023-10-10
申请号：US17514847
申请日：2021-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
CPC classification number: G11C27/005 , G11C15/046
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
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公开(公告)号：US11735281B2
公开(公告)日：2023-08-22
申请号：US17245540
申请日：2021-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , Can Li , John Paul Strachan
CPC classification number: G11C27/005 , G11C15/046
Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11615827B2
公开(公告)日：2023-03-28
申请号：US17071924
申请日：2020-10-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , Can Li , Kivanc Ozonat , John Paul Strachan
IPC: G11C15/04 , G11C11/00 , G06F9/38 , G11C11/06 , G11C11/412
Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.
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公开(公告)号：US20210225440A1
公开(公告)日：2021-07-22
申请号：US17223435
申请日：2021-04-06
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Amit S. Sharma , John Paul Strachan , Catherine Graves , Suhas Kumar , Craig Warner , Martin Foltin
Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
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公开(公告)号：US10984860B2
公开(公告)日：2021-04-20
申请号：US16364717
申请日：2019-03-26
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Amit S. Sharma , John Paul Strachan , Catherine Graves , Suhas Kumar , Craig Warner , Martin Foltin
Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
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公开(公告)号：US10452472B1
公开(公告)日：2019-10-22
申请号：US15997030
申请日：2018-06-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , John Paul Strachan , Dejan S. Milojicic , Paolo Faraboschi , Martin Foltin , Sergey Serebryakov
Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.
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公开(公告)号：US12272401B2
公开(公告)日：2025-04-08
申请号：US18308990
申请日：2023-04-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ron M. Roth , Luca Buonanno , Giacomo Pedretti , Catherine Graves
Abstract: Systems and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). An example of a TCAM comprises a match line, and a plurality of TCAM cells connected along the match line. Each TCAM cell stores a state of a threshold value. The TCAM cells are configured to pull down a signal over the match line in response to inequality between an input search and the threshold value. The plurality of TCAM cells comprises a number of TCAM cells that is less than the threshold value. The input values can be encoded according to a first encoding scheme and the threshold value can be encoded according to one of a second and a third encoding scheme based on an inequality check mapped to the plurality of TCAM cells.
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