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    CONFIGURATION OF CONFIGURABLE TEST LOGIC
    1.
    发明公开
    CONFIGURATION OF CONFIGURABLE TEST LOGIC 审中-公开

    公开(公告)号：US20240019490A1

    公开(公告)日：2024-01-18

    申请号：US17812937

    申请日：2022-07-15

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Naysen J. Robertson ,  Christopher M. Wesneski ,  Samuel Gonzalez

    IPC: G01R31/317 ,  G01R31/3185

    CPC classification number: G01R31/31727 ,  G01R31/3185

    Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

    RESTORING STATES OF REAL TIME CLOCK DEVICES FOR MULTIPLE HOSTS
    2.
    发明公开
    RESTORING STATES OF REAL TIME CLOCK DEVICES FOR MULTIPLE HOSTS 审中-公开

    公开(公告)号：US20240111639A1

    公开(公告)日：2024-04-04

    申请号：US18452603

    申请日：2023-08-21

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Christopher M. Wesneski ,  Theodore F. Emerson

    IPC: G06F11/14 ,  G06F1/14

    CPC classification number: G06F11/1469 ,  G06F1/14

    Abstract: A process includes, responsive to a primary power source being enabled, receiving, from a real time clock (RTC) device of a computer platform, an indication of a first time. Responsive to the primary power source being enabled, the process includes storing first data in a first non-volatile storage of the computer platform representing a snapshot of the first time and repeatedly updating the snapshot to cause the snapshot to track the first time. Responsive to the primary power source being disabled to begin a power outage, the process includes providing, by a timer of the computer platform powered by a secondary power source, a timer output that represents an accumulated time that corresponds to the power outage. The process includes restoring a state of the RTC device responsive to the primary power source being reenabled to end the power outage. The restoration includes, based on the accumulated time and the snapshot, determining a second time, and storing second data in the RTC device that represents the second time.

    Configuration of configurable test logic
    3.
    发明授权
    Configuration of configurable test logic 有权

    公开(公告)号：US11899066B2

    公开(公告)日：2024-02-13

    申请号：US17812937

    申请日：2022-07-15

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Naysen J. Robertson ,  Christopher M. Wesneski ,  Samuel Gonzalez

    IPC: G01R31/3185 ,  G06F30/34 ,  G01R31/317

    CPC classification number: G01R31/3185 ,  G06F30/34 ,  G01R31/31727

    Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

    TIMESTAMPING TAMPERING EVENTS THAT OCCUR DURING PRIMARY POWER OUTAGES
    9.
    发明公开
    TIMESTAMPING TAMPERING EVENTS THAT OCCUR DURING PRIMARY POWER OUTAGES 审中-公开

    公开(公告)号：US20240111912A1

    公开(公告)日：2024-04-04

    申请号：US18452608

    申请日：2023-08-21

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Christopher M. Wesneski ,  Theodore F. Emerson

    IPC: G06F21/86 ,  G06F1/14

    CPC classification number: G06F21/86 ,  G06F1/14

    Abstract: A process includes performing actions responsive to secondary power when primary power for a computer platform is unavailable. The actions include providing, by a timer of a computer platform, a timer output that is associated with a first time domain and corresponds to an accumulated time that primary power is unavailable. Moreover, these actions include using secondary power to detect tampering with the computer platform, and responsive to detecting the tampering, reading the timer output to provide a first timestamp that represents a time of detection of the tampering. The process further includes actions which are performed responsive to primary power being subsequently available. These actions include reading data from a non-volatile storage of the computer platform. The data represents a snapshot of a real time clock (RTC) device time that is provided by an RTC device that is powered by the primary power and corresponds to a second time domain. The actions further include transforming the first timestamp into a second timestamp associated with the second time domain based on the snapshot.

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