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公开(公告)号：US11424859B2
公开(公告)日：2022-08-23
申请号：US17071843
申请日：2020-10-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Christopher Michael Brueggen , James Donald Regan , Elene Chobanyan
Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.
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公开(公告)号：US20240055157A1
公开(公告)日：2024-02-15
申请号：US18491907
申请日：2023-10-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Karl J. Bois , James David Stewart , David P. Kopp , Elene Chobanyan
IPC: H01B11/18 , H01P3/06 , H01B13/016
CPC classification number: H01B11/1808 , H01B11/1856 , H01P3/06 , H01B13/0167 , H01R12/75
Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.
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公开(公告)号：US11042683B2
公开(公告)日：2021-06-22
申请号：US15217226
申请日：2016-07-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois
IPC: G06F30/398
Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.
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公开(公告)号：US20200236777A1
公开(公告)日：2020-07-23
申请号：US16252016
申请日：2019-01-18
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois , Christian Olsen
Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.
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公开(公告)号：US10445458B2
公开(公告)日：2019-10-15
申请号：US15280906
申请日：2016-09-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Elene Chobanyan , Karl J Bois , Charles Andrew Hartman
Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.
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Patent Agency Ranking
公开(公告)号：US11810689B2
公开(公告)日：2023-11-07
申请号：US17068344
申请日：2020-10-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Karl J. Bois , James David Stewart , David P. Kopp , Elene Chobanyan
CPC classification number: H01B11/1808 , H01B11/1856 , H01B13/0167 , H01P3/06 , H01R12/722 , H01R12/75
Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.
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公开(公告)号：US11191152B2
公开(公告)日：2021-11-30
申请号：US16252016
申请日：2019-01-18
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois , Christian Olsen
Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.
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公开(公告)号：US10356964B2
公开(公告)日：2019-07-16
申请号：US15215982
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois , Dave Mayer , Arlen L. Roesner
Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.
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公开(公告)号：US20180026325A1
公开(公告)日：2018-01-25
申请号：US15215982
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois , Dave Mayer , Arlen L. Roesner
CPC classification number: H05K9/0007 , H01P1/30 , H01P5/024 , H05K9/0041
Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.
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公开(公告)号：US20180025106A1
公开(公告)日：2018-01-25
申请号：US15217226
申请日：2016-07-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Elene Chobanyan , Karl J. Bois
IPC: G06F17/50
CPC classification number: G06F17/5081
Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.
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