公开(公告)号：US11360782B2

公开(公告)日：2022-06-14

申请号：US16779230

申请日：2020-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen Robertson ,  Kenneth T. Chin ,  Theodore F. Emerson

IPC: G06F9/44 ,  G06F9/4401 ,  G06F21/57

Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

公开(公告)号：US20210240646A1

公开(公告)日：2021-08-05

申请号：US16779184

申请日：2020-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen Robertson ,  Kenneth T. Chin ,  Theodore F. Emerson

IPC: G06F13/362 ,  G06F13/16 ,  G06F9/38 ,  G06F9/54 ,  G06F9/445 ,  G06F9/4401 ,  G06F13/28

Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

公开(公告)号：US20180287621A1

公开(公告)日：2018-10-04

申请号：US15475243

申请日：2017-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Christopher Wesneski ,  Theodore F. Emerson ,  Kenneth T. Chin

IPC: H03L7/099 ,  H03L7/081

CPC classification number: H03K5/135 ,  H03L7/1976

Abstract: An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.

公开(公告)号：US20210240485A1

公开(公告)日：2021-08-05

申请号：US16779230

申请日：2020-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen Robertson ,  Kenneth T. Chin ,  Theodore F. Emerson

IPC: G06F9/4401 ,  G06F21/57

Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.

公开(公告)号：US20180074777A1

公开(公告)日：2018-03-15

申请号：US15565225

申请日：2015-05-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Theodore F. Emerson ,  David F. Heinrich ,  Kenneth T. Chin

IPC: G06F3/14 ,  H04N21/2365 ,  H04N21/242 ,  G06T1/60

CPC classification number: G06F3/1438 ,  G06T1/60 ,  G09G2352/00 ,  G09G2360/12 ,  G09G2370/24 ,  H04N5/76 ,  H04N21/2365 ,  H04N21/242 ,  H04N21/42653

Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.

公开(公告)号：US11138140B2

公开(公告)日：2021-10-05

申请号：US16779184

申请日：2020-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naysen Robertson ,  Kenneth T. Chin ,  Theodore F. Emerson

IPC: G06F13/362 ,  G06F13/28 ,  G06F13/16 ,  G06F9/54 ,  G06F9/445 ,  G06F9/38 ,  G06F9/4401

Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

公开(公告)号：US10404244B2

公开(公告)日：2019-09-03

申请号：US15475243

申请日：2017-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Christopher Wesneski ,  Theodore F. Emerson ,  Kenneth T. Chin

IPC: H03K5/135 ,  H03L7/197

Abstract: An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.

公开(公告)号：US10372400B2

公开(公告)日：2019-08-06

申请号：US15565225

申请日：2015-05-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Theodore F. Emerson ,  David F. Heinrich ,  Kenneth T. Chin

IPC: G09G5/36 ,  G06F3/14 ,  H04N5/76 ,  G06T1/60 ,  H04N21/2365 ,  H04N21/242 ,  H04N21/426

Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.